Datasheet

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SLAS370C − APRIL 2002 − REVISED OCTOBER 2004
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INTERNAL USER-ACCESSIBLE REGISTERS
The registers in the ADS7871 are eight bits wide. Most of the registers are reserved, the ten user-accessible
registers are summarized in the register address map (see Figure 18). Detailed information for each register
follows. The default power-on/reset state of all bits in the registers is 0.
ADC Output Registers
The A/D Output registers are read only registers located at ADDR = 0 and ADDR = 1 that contain the results
of the A/D conversion, ADC13 through ADC0 (see Figure 25). The conversion result is in 2s complement
format. The bits can be taken out of the registers MSB (D7) first or LSB (D0) first, as determined by the state
of the LSB bits (D7 or D0) in the Serial Interface Control register. The ADDR = 0 register also contains the OVR
bit which indicates if the internal voltage limits to the PGA have been exceeded.
ADC OUTPUT REGISTERS
ADDR D7 (MSB) D6 D5 D4 D3 D2 D1 D0
0 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 0 OVR
1 ADC13 ADC12 ADC11 ADC10 ADC9 ADC8 ADC7 ADC6
ADDR = 0 (LS Byte)
BIT SYMBOL NAME VALUE FUNCTION
D7−D2 ADC5−ADC0 A/D Output (1) Six least significant bits of conversion result
D1 — — 0 This bit is not used and is always 0.
D0 OVR PGA Over-Range 0
1
Valid conversion result
An analog over-range problem has occurred in the PGA. Conversion result
may be invalid. Details of the type of problem are stored in register 2, the
PGA Valid register.
ADDR = 1 (MS Byte)
BIT SYMBOL NAME VALUE FUNCTION
D7−D0 ADC13−ADC6 ADC Output (1) Eight most significant bits of conversion result
(1)
Value depends on conversion result
Figure 25. ADC Output Registers (ADDR = 0 and ADDR = 1)