Datasheet


SLAS370C − APRIL 2002 − REVISED OCTOBER 2004
www.ti.com
17
Note that the seven lower bits of this byte are written to register 4, the Gain/Mux register.
All other controllable ADS7871 parameters are values previously stored in their respective registers. These
values are either the power-up default values (0) or values that were previously written to one of the control
registers in a register mode operation. No additional data is required for a direct mode instruction.
Register Mode
In register mode (bit D7 of the instruction byte is 0) a read or write instruction to one of the ADS7871 registers
is initiated. All of the user determinable functions and features of the ADS7871 can be controlled by writing
information to these registers (see Figure 21). Conversion results can be read from the A/D Output registers.
REGISTER ADDRESS
ADDR
READ/
REGISTER CONTENT
A4 A3 A2 A1 A0
ADDR
NO.
READ/
WRITE
D7(MSB) D6 D5 D4 D3 D2 D1 D0
REGISTER NAME
0 0 0 0 0 0 Read ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 0 OVR A/D Output Data, LS Byte
0 0 0 0 1 1 Read ADC13 ADC12 ADC11 ADC10 ADC9 ADC8 ADC7 ADC6 A/D Output Data, MS Byte
0 0 0 1 0 2 Read 0 0 VLD5 VLD4 VLD3 VLD2 VLD1 VLD0 PGA Valid Register
0 0 0 1 1 3 R/W 0 0 BIN 0 RMB1 RBM0 CFD1 CFD0 A/D Control Register
0 0 1 0 0 4 R/W CNV/BSY G2 G1 G0 M3 M2 M1 M0 Gain/Mux Register
0 0 1 0 1 5 R/W CNV/BSY 0 0 0 IO3 IO2 IO1 IO0 Digital I/O State Register
0 0 1 1 0 6 R/W 0 0 0 0 OE3 OE2 OE1 OE0 Digital I/O Control Register
0 0 1 1 1 7 R/W 0 0 OSCR OSCE REFE BUFE R2V RBG
Ref/Oscillator Control
Register
1 1 0 0 0 24 R/W LSB 2W/3W 8051 0 0 8501 2W/3W LSB
Serial Interface Control
Register
1 1 1 1 1 31 Read 0 0 0 0 0 0 0 1 ID Register
Figure 18. Register Address Map
The instruction byte (see Figure 17) contains the address of the register for the next read/write operation,
determines whether the serial communication is to be done in 8-bit or 16-bit word length, and determines
whether the next operation is read-from or written-to the addressed register.
The structure of the instruction byte for register mode is shown in Figure 17.
D D7: This bit is set to 0 for register mode operation.
D D6 (R/W): Bit 6 of the instruction byte determines whether a read or write operation is performed, 1 for
a read or 0 for a write.
D D5 (16/8): This bit determines the word length of the read or write operation that follows, 1 for sixteen bits
(two eight-bit bytes) or 0 for eight bits.
D D4 through D0 (A4 − A0): These bits determine the address of the register that is to be read from or written
to. Register address coding and other information are tabulated in Figure 18.
For 16-bit operations, the first eight bits are written-to/read-from the address encoded by the instruction byte,
bits A4 through A0 (register address). The address of the next eight bits depends upon whether the register
address for the first byte is odd or even. If it is even, then the address for the second byte is the register address
+ 1. If the register address is odd, then the address for the second byte is the register address – 1.
This arrangement allows transfer of conversion results from the two A/D Output Data registers either MS byte
first or LS byte first (refer to the section Serial Interface Control Register).
Register Summary
A summary of information about the addressable registers is shown in Figure 18. Their descriptions follow, and
more detailed information is provided later in the section Internal User-accessible Registers.
Registers 0 and 1, the A/D Output Data registers, contain the least significant and most significant bits of the
A/D conversion result (ADC0 through ADC13). Register 0 also has one fixed zero (D1), and a bit to indicate
if the internal voltage limits of the PGA have been over ranged (OVR). This is a read only register. Write an 8-bit
word to register 0 and the ADS7871 is reset.