Datasheet

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SLAS370C − APRIL 2002 − REVISED OCTOBER 2004
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16
Operating Modes
The ADS7871 serial interface operates based on an instruction byte followed by an action commanded by the
contents of that instruction. The 8-bit instruction word is clocked into the DIN input. There are two types of instruction
bytes that may be written to the ADS7871 as determined by bit D7 of the instruction word (see Figure 17). These
two instructions represent two different operating modes. In direct mode (bit D7 = 1), a conversion is started. A
register mode (bit D7 = 0) instruction is followed by a read or write operation to the specified register.
OR
D7 (MSB) D6 D5 D4 D3 D2 D1 D0
G21G1G0M3M2M1M0
R/W
0 16/8 A4 A3 A2 A1 A0
Start Conversion
(Direct Mode)
Read/Write
(Register Mode)
INSTRUCTION BYTE
START CONVERSION INSTRUCTION BYTE (Direct Mode)
(1)
BIT SYMBOL NAME VALUE FUNCTION
D7 Mode select 1 Starts a conversion cycle (direct mode)
D6−D4 G2−G0 PGA gain select 000
001
010
011
100
101
110
111
PGA Gain = 1 (power up default condition)
PGA Gain = 2
PGA Gain = 4
PGA Gain = 5
PGA Gain = 8
PGA Gain = 10
PGA Gain = 16
PGA Gain = 20
D3−D0 M3−M0 Input channel select See Figure 24 Determines input channel selection for the requested conversion,
differential or single-ended configuration.
(1)
The seven lower bits of this byte are also written to register 4, the Gain/Mux register.
READ/WRITE INSTRUCTION BYTE (Register Mode)
BIT SYMBOL NAME VALUE FUNCTION
D7 Mode Select 0 Initiates a read or write operation (register mode)
D6 R/W Read/Write Select 0
1
Write operation
Read operation
D5 16/8 Word Length 0
1
8-Bit word
16-Bit word (2 8-bit bytes)
D4−D0 AS4−AS0 Register Address See Figure 18 Determines the address of the register that is to be read from or written to
Figure 17. Instruction Byte Addressing
Direct Mode
In direct mode a conversion is initiated by writing a single 8-bit instruction byte to the ADS7871 (bit D7 is set
to 1). Writing the direct mode command sets the configuration of the multiplexer, selects the gain of the PGA,
and starts a conversion cycle. After the last bit of the instruction byte is received, the ADS7871 performs a
conversion on the selected input channel with the PGA gain set as indicated in the instruction byte.
The conversion cycle begins on the second falling edge of DCLK after the eighth active edge of SCLK of the
instruction byte. When the conversion is complete, the conversion result is stored in the A/D Output registers
and is available to be clocked out of the serial interface by the controlling device using the READ operation in
the register mode.
The structure of the instruction byte for direct mode is shown in Figure 17.
D D7: This bit is set to 1 for direct mode operation
D D6 through D4 (G2 − G0): These bits control the gain of the programmable gain amplifier. PGA gains of 1,
2, 4, 5, 8, 10,16, and 20 are available. The coding is shown in Figure 17.
D D3 through D0 (M3 − M0): These bits configure the switches that determine the input channel selection.
The input channels may be placed in either differential or single-ended configurations. In the case of
differential configuration, the polarity of the input signal is reversible. The coding is shown in Figure 27.