Datasheet

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SLAS370C − APRIL 2002 − REVISED OCTOBER 2004

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FUNCTIONAL DESCRIPTION

Multiplexer

The ADS7871 has eight analog signal input pins, LN0 through LN7. These pins are connected to a network of

analog switches (the MUX block in the block diagram). The switches are controlled by four bits in the Gain/Mux

LN0 through LN7 can be configured as 8 single-ended inputs or 4 differential inputs or some other combination.

Some MUX combination examples are shown in Figure 23. The differential polarity of the input pins can be

changed with the M2 bit in the MUX address. This feature allows reversing the polarity of the conversion result

without having to physically reverse the input connections to the ADS7871.

For linear operation, the input signal at any of the LN0 through LN7 pins can range between GND – 0.2 V and

+ 0.2 V. The polarity of the differential signal can be changed through commands written to the Gain/Mux

Inputs LN0 through LN7 have ESD protection circuitry as the first active elements on the chip. These contain

protection diodes connected to VDD and GND that remain reverse biased under normal operation. If input

voltages are expected beyond the absolute maximum voltage range, it is necessary to add resistance in series

with the input to limit the current to 10 mA or less.

Conversion Clock

The conversion clock (CCLK) and signals derived from it are used by the voltage reference, the PGA, and the

A/D converter. The CCLK pin can be made either an input or an output. For example, one ADS7871 can be

made to be the conversion clock master (CCLK is an output), while the others are slaved to it with their CCLK

pins all being inputs (by default). This can reduce A/D conversion errors caused by multiple clocks and other

systems noise.

When the OSC ENABLE pin is low or zero, the CCLK pin is an input and the ADS7871 relies on an applied external

clock for the conversion process. When OSC ENABLE is high or if the OSCE bit D4 in register 7 is set to a one,

the internal oscillator and an internal buffer is enabled, making pin 19 an output. Either way the CCLK is sensed

internally at the pin so all ADS7871s see the same clock delays. Capacitive loading on the CCLK pin can draw

significant current compared with the supply current to the ADS7871 (I

LOAD

= f

CCLK

× V

× C

LOAD

The internal reference requires a continuous clock and may be supplied by the internal oscillator independently

of the system clock driving the CCLK pin. Setting OSCR (bit D5 in register 7) and REFE (bit D3 in register 7)

both to one accomplishes this. Figure 11 illustrates all of these relationships.

The ADS7871 utilizes the power saving technique of turning on and off the biasing for the PGA and A/D as

needed. This does not apply to the oscillator, reference, and buffer, these run continuously when enabled. The

buffer output is high impedance when disabled, so for a low power data logging application the filter capacitor

is not discharged when the buffer is turned off and does not require as much settling time when turned on.

The serial interface clock is independent of the conversion clock and can run faster or slower. If it is desirable

to use a faster system clock than the 2.5-MHz nominal rate that the ADS7871 uses then this clock may be

divided to a slower rate ( 1/2, 1/4, 1/8) by setting the appropriate bits in register 3. This clock divider applies

equally to an external as well as internal clock to create the internal DCLK for the PGA and A/D conversion cycle.

The ADS7871 has both maximum and minimum DCLK frequency constraints (DCLK = CCLK/DF). The

maximum DCLK is 2.5 MHz. The minimum DCLK frequency applied to the PGA, reference, and A/D is 100 kHz.