Datasheet

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SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
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29
Serial Interface Timing (8051 Bit)
The 8051 bit changes the timing of when the DIN pin goes to high impedance at the end of an operation. When
the bit is a 1, the pin goes to high impedance on the last active SCLK edge of the last byte of data transfer instead
of waiting for the next inactive edge, or CS
to go inactive. This allows the ADS7870 to disconnect from the data
lines soon enough to avoid contention with an 80C51-type interface. The 80C51 drives data four CPU cycles before
an inactive SCLK edge and for two CPU cycles after an active SCLK edge. When the 8051 bit is a 0, the DIN pin
goes high impedance on the next inactive SCLK edge or when CS goes inactive (1).
Figure 30 and Figure 31 show the timing of when the ADS7870 sets the DIN pin to high impedance at the end
of a read operation when the 2W/3W bit is set. The behavior of DOUT does not depend of the state of 2W/3W.
The 8051 bit is not set for these two examples.
A0 A1 A2 A3 A4
01
0 D0D1D2D3D4D5D6D7
D3 D4 D5 D6 D7
Micro drives DIN
ADS7870 drives DIN DIN high−impedance on CS
D0 D1 D2
SCLK
DIN
DOUT
CS
Figure 30. Timing for High Impedance State on DIN/DOUT (CS = 1)
A0
A3 1
0D0D1D2D3 D7
D0
D1 D4
D5
D6
D7
Micro drives DIN
ADS7870 drives DIN DIN high−impedance on inactive edge
D4
D5 D6
A4 0
D2 D3
A1
A2
SCLK
DIN
DOUT
CS
Figure 31. Timing for High Impedance State on DIN/DOUT (Inactive SCLK Edge)