Datasheet

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SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
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22
PGA Valid Register
The PGA Valid register (ADDR = 2) is a read only register that contains the individual results of each of the six
comparators for the PGA, VLD5 through VLD0, as shown in Figure 23.
PGA VALID REGISTER
ADDR D7 (MSB) D6 D5 D4 D3 D2 D1 D0
2 0 0 VLD5 VLD4 VLD3 VLD2 VLD1 VLD0
ADDR = 2
BIT SYMBOL NAME VALUE FUNCTION
D7−D6 — — 0 These bits are not used and are always 0.
D5 VLD5 PGA Valid 5 0
1
0 − Voltage at minus (−) output from the PGA is within its minimum value.
1 − Voltage at minus (−) output from the PGA has exceeded its minimum value.
D4 VLD4 PGA Valid 4 0
1
0 − Voltage at minus (−) output from the PGA is within its maximum value.
1 − Voltage at minus (−) output from the PGA has exceeded its maximum value.
D3 VLD3 PGA Valid 3 0
1
0 − Voltage at minus (−) input to the PGA is within its maximum value.
1 − Voltage at minus (−) input to the PGA has exceeded its maximum value.
D2 VLD2 PGA Valid 2 0
1
0 − Voltage at plus (+) output from the PGA is within its minimum value.
1 − Voltage at plus (+) output from the PGA has exceeded its minimum value.
D1 VLD1 PGA Valid 1 0
1
0 − Voltage at plus (+) output from the PGA is within its maximum value.
1 − Voltage at plus (+) output from the PGA has exceeded its maximum value.
D0 VLD0 PGA Valid 0 0
1
0 − Voltage at plus (+) input to the PGA is within its maximum value.
1 − Voltage at plus (+) input to the PGA has exceeded its maximum value.
Bold items are power-up default conditions.
Figure 23. PGA Valid Register (ADDR = 2)