Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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3.9 Interrupt
The interrupt can have several sources:
• FIFO full status
• FIFO empty status
• Two TIMECOUNT over- or under-flows
• Two EDGECOUNT over- or under-flows
These six sources are combined into one interrupt signal. The interrupt signal is active high; when the interrupt
pin INT is high, one of the six sources is also high.
To reset an interrupt, the Interrupt Register must be read (see Interrupt Register section), in order to allow the
host to determine which source, or sources, caused the interrupt.
3.10 Reset
The ADS7869 can be forced into a reset state in three different ways:
• Power-on.
• Pulling the RST
pin (reset pin 79) low.
• Writing to the Reset Register.
In addition, the digital counters can be reset via the Reset Register, without resetting the entire ADS7869.
In a reset state, the analog inputs are sampled, the registers (in the register map) are forced into their reset
values, and the FIFO and the counters are cleared. One rising clock pulse during a reset condition is
necessary to reset the synchronous counters.
It takes one clock cycle for the ADS7869 to begin the normal operation after the last reset condition is cleared.
(See Figure 1−29.)
3.10.1 Reset Timing Characteristics
(1)
Over recommended operating free-air temperature range at –40_C to +85_C, AV
DD
= 5V, BV
DD
= 3V − 5V.
PARAMETER
SYMBOL MIN MAX UNIT
Setup time from RST LOW to rising CLK t
SU1
10 ns
Hold time from rising CLK to RST HIGH t
H1
5 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of BV
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
CLK
RST
t
H1
t
SU1
Figure 1−29. Timing Diagram of the Reset Signal RST