Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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51
3.7.1 DAV Timing Characteristics
(1)
Over recommended operating free-air temperature range at –40_C to +85_C, AV
DD
= 5V, BV
DD
= 3V − 5V.
PARAMETER
SYMBOL MIN MAX UNIT
Delay time from 14th rising CLK to falling DAV
(2)
t
D1
50 ns
Setup time from RD HIGH to next rising CLK t
SU1
8 ns
Delay time from rising CLK to rising DAV
(2)(3)
t
D2
50 ns
Setup time from CS HIGH to next rising CLK t
SU2
8 ns
Delay time from rising CLK to rising DAV
(2)(3)
t
D3
50 ns
Setup time from SPISTE HIGH to next rising CLK t
SU3
8 ns
Delay time from rising CLK to rising DAV
(2)(3)
t
D4
50 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of BV
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) With the DAV bit in the Control register (14
H
), the DAV signal can have opposite polarity.
(3) Only applicable when the last data is read from the FIFO
(1) Parallel mode 11.
(2) Parallel mode 10 and TMS320C54xx mode.
(3) SPI mode.
CLK 1 2 3 4 12 13 14 15
t
D1
HOLD
DAV
CS
(1)
RD
(1)
DAV
(1)
CLK
CS
(2)
DAV
(2)
SPISTE
(3)
DAV
(3)
t
SU1
t
SU2
t
D3
t
SU3
t
D4
t
D2
Figure 1−22. Timing of the DAV Signal