Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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The DAV signal becomes active when the write pointer is ahead of the read pointer. The DAV signal becomes
inactive again when the read pointer equals the write pointer (that is, when the FIFO is empty).
When the ADCs are writing data into the FIFO, and the write pointer is more than 32 steps ahead of the read
pointer, a FF (FIFO Full) state will be set. FF is cleared when the first FIFO read operation is performed. To
synchronize the pointers after an FF state, the FIFO should be read out until a FE (FIFO Empty) occurs.
If a read is attempted, while the read and write pointers are equal, the read pointer will not increase; the same
data (the data with the same channel number) is read again. When this occurs, an FE state is set. The FE
state is cleared when new data is written into the FIFO. The read pointer will not go beyond the write pointer.
Both FF and FE go into the Interrupt section. The functional block diagram of the FIFO is shown in Figure 1−21.
The purpose of the test data is to verify the FIFO structure for the development of an application. This is
described in the FIFO Test Register section. This register should not be used in normal operation.
READ ADC
FIFO CONTROL
FIFO_FULL INT
FIFO_EMPTY
DAV
READ and WRITE
POINTER
FIFO MEMORY
32 x 16
FIFO
SHIFT
REGISTER
ADC BUSY
TEST CLOCK
TEST ENABLE
ADC1
ADC2
ADC3
TEST DATA
Figure 1−21. FIFO Block Diagram