Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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49
3.7 FIFO
The FIFO of the ADS7869 is organized as a 32-word ring buffer with 16 bits per word, shown in Figure 1−20.
Read Pointer
Write Pointer
Data in FIFO
Free
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1617
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Figure 1−20. FIFO Structure
The converted data of the ADS7869 is automatically written into the FIFO. To control the writing and reading
process, a write pointer and a read pointer are used. The read pointer always shows the location that contains
the last read data. The write pointer indicates the location that contains the last written sample. The converted
values are written in a predefined sequence to the circular buffer, beginning with ADC
1
and ending with ADC
3
.
The channel number is stored with the ADC data. The data of the FIFO is read through the FIFO register at
address 00
H
; its format is presented in Table 1−27. The table shows that the channel information for the
converted channel data, is continually maintained. The address 00
H
in the register map shows only the data
to which the read pointer is directed.
The FIFO generates the DAV signal; see Figure 1−22 on page 51. In VECANA mode, this signal is low; it
indicates that the ADS7869 is converting data (see Figure 1−10 on page 26). In the other modes, the DAV
indicates that data in the FIFO is available. The DAV signal can be configured as either a positive or negative
signal; see the Control Register section.
Table 1−27. FIFO 16-bit Data Read Format
ADDRESS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
00
H
0 0 0 0 ADC
1
value, channel IU, included offset and gain compensation
00
H
0 0 0 1 ADC
1
value, channel A1, included offset and gain compensation
00
H
0 0 1 0 ADC
1
value, channel A2, included offset and gain compensation
00
H
0 0 1 1 ADC
2
value, channel IV, included offset and gain compensation
00
H
0 1 0 0 ADC
2
value, channel B1, included offset and gain compensation
00
H
0 1 0 1 ADC
2
value, channel B2, included offset and gain compensation
00
H
0 1 1 0 ADC
3
value, channel IW, included offset and gain compensation
00
H
0 1 1 1 ADC
3
value, channel AN1, included offset and gain compensation
00
H
1 0 0 0 ADC
3
value, channel AN2, included offset and gain compensation
00
H
1 0 0 1 ADC
3
value, channel AN3, included offset and gain compensation
00
H
1 0 1 0 ADC
1
value, channel AX, included offset and gain compensation
00
H
1 0 1 1 ADC
2
value, channel BX, included offset and gain compensation
00
H
1 1 0 0 Not existing
00
H
1 1 0 1 Not existing
00
H
1 1 1 0 Not existing
00
H
1 1 1 1 Not existing