Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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47
Interrupt Register, continued
Bit 5: FF: FIFO full state
1 = FIFO is full
0 = FIFO is not full
Bit 4: FE: FIFO empty state
1 = FIFO is empty
0 = FIFO is not empty
Bit 3: FFF: FIFO full flag
1 = FIFO is or was full
0 = FIFO is not or was not full
Bit 2: FEF: FIFO empty flag
1 = FIFO is or was empty
0 = FIFO is not or was not empty
Bit 1 FFE: FIFO full interrupt enable bit
1 = Interrupt enable
0 = Interrupt disable
Bit 0: FEE: FIFO empty interrupt enable bit
1 = Interrupt enable
0 = Interrupt disable
3.6.13 Parallel Register (27
H
)
The Parallel Register, in address 27
H
, controls the parallel interface mode 11; see the Mode 11 Bus Access
sections. The Parallel Register has no effect on modes 00, 01, and 10. There is only one bit present in the
Parallel Register, the M bit. The format of the Parallel Register is shown in Table 1−25.
Table 1−25. Parallel Register
R0
R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 RW1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Bit 15−1: Unused (read as ‘0’)
Bit 0: M: Set up the type of the parallel interface
1 = Parallel interface, mode 11 (default)
0 = TMS320c54xx DSP family-compatible parallel interface