Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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46
3.6.12 Interrupt Register (26
H
)
The Interrupt Register, in address 26
H
, contains the interrupt source and interrupt control bits. The bits xOxF
are set when a particular counter had an over- or under-flow. The bits remain set until the Interrupt Register
is read; this is independent of whether the counter over- or under-flow states remain or not. The counter over-
or under-flow interrupt is enabled when the appropriate xOxE bits are set.
The FFF bit, FIFO full flag, will be set when the FIFO is (or was) full and remains set until the Interrupt Register
is read, independent of whether the FIFO is full or not. The FF bit, FIFO full, indicates whether the FIFO is
full or not. The FFF bit is cleared when the Interrupt Register is read. The FIFO full interrupt is enabled when
the bit FFE (or FIFO full enable) is set.
The FEF bit, FIFO empty flag, will be set when the FIFO is (or was) empty and remains set until the Interrupt
Register is read, independent of whether the FIFO is empty or not. The FE bit, FIFO empty, indicates if the
FIFO is empty or not. The bit FEF is cleared when the Interrupt Register is read. The FIFO empty interrupt
is enabled when the FEE bit , FIFO empty enable, is set. For more information about the Interrupt pin, see
the Interrupt section. Table 1−24 describes the Interrupt Register.
Table 1−24. Interrupt Register
RW0
RW0 RW0 RW0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 RW0 RW0
EO2E TO2E EO1E TO1E EO2F TO2F EO1F TO1F 0 0 FF FE FFF FEF FFE FEE
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Bit 15: EO2E: Edge counter 2, EDGECNT2, over- or under-flow interrupt enable bit
1 = Interrupt enable
0 = Interrupt disable
Bit 14: TO2E: Time counter 2, TIMECOUNT2, over- or under-flow interrupt enable bit
1 = Interrupt enable
0 = Interrupt disable
Bit 13: EO1E: Edge counter 1, EDGECNT1, over- or under-flow interrupt enable bit
1 = Interrupt enable
0 = Interrupt disable
Bit 12: TO1E: Time counter 1, TIMECOUNT1, over- or under-flow interrupt enable bit
1 = Interrupt enable
0 = Interrupt disable
Bit 11: EO2F: Edge counter 2, EDGECNT2, over- or under-flow flag
1 = EDGECNT2 over- or under-flow occurred
0 = EDGECNT2 over- or under-flow did not occur
Bit 10: TO2F: Time counter 2, TIMECOUNT2, over- or under-flow flag
1 = TIMECOUNT2 over- or under-flow occurred
0 = TIMECOUNT2 over- or under-flow did not occur
Bit 9: EO1F: Edge counter 1, EDGECNT1, over- or under-flow flag
1 = EDGECNT1 over- or under-flow occurred
0 = EDGECNT1 over- or under-flow did not occur
Bit 8: TO1F: Time counter 1, TIMECOUNT1, over- or under-flow flag
1 = TIMECOUNT1 over- or under-flow occurred
0 = TIMECOUNT1 over- or under-flow did not occur
Bit 7−6: Unused (read as ‘0’)