Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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44
3.6.9 Edge Time Period Register (1F
H
and 23
H
)
There are two read-only shadow registers for the two edge time counters. The registers SYEDGTIME1 and
SYEDGTIME2, synchronous edge time 1 (in address 1F
H
) and synchronous edge time 2 (in address 23
H
),
latch the values from the edge time counters when the synchronous hold signal HOLD1
is set to low. The Edge
Time Register is described in Table 1−21.
Table 1−21. Edge Time Period Register
R0
R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Bit 15−0: D15−0: The 16 bits of the synchronous latched edge time counters
3.6.10 FIFO Test Register (24
H
)
The purpose of the FIFO Test Register, in address 24
H
, is to test the FIFO during production test; the FIFO
is filled with a defined pattern via this register. The internal FIFO structure can be verified by reading the
patterns of the FIFO data register. When the FIFO test is enabled, the multiplexers are switched and lead the
data (of the FIFO test register) into the FIFO, instead of the normal ADC data; to simulate the three ADCs,
the data is latched into the FIFO three times. To distinguish between the channels, the first data is unchanged
to simulate ADC
1
, the second data is inverted to simulate ADC
2
, and the six LSBs of the third data are inverted
to simulate ADC
3
. While the FIFO test is enabled, a total of three data words will be stored in the FIFO, with
one write instruction. In order to fill the entire FIFO register with test data, 10 writes must be performed. The
test data is written into the FIFO only when the four enable bits have the value A
H
. This register should not
be used in normal operation. The format of the output word is shown in Table 1−22.
Table 1−22. FIFO Test Register
RW0
RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0
E3 E2 E1 E0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Bit 15−12: E3−0: Input channel address bits
0000 = Disable FIFO test
...
1001 = Disable FIFO test
1010 = Enable FIFO test write procedure
1011 = Disable FIFO test
...
1111 = Disable FIFO test
Bit 11−0: DATA11−0: The input data that will be written into the FIFO registers
In FIFO test mode the four channel bits are copied from Bit 11 of the written data.