Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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43
3.6.7 Edge Count Register (1C
H
, 1D
H
, 20
H
and 21
H
)
There are four shadow registers for the two edge counters. The registers SYEDGCNT1 and SYEDGCNT2,
synchronous edge count 1 (in address 1D
H
), and synchronous edge count 2 (in address 21
H
), latch the values,
from the edge counters, when the synchronous hold signal HOLD1
is set to low.
Registers ASEDGCNT1, ASEDGCNT2, asynchronous edge count 1 (in address 1C
H
), and asynchronous
edge count 2 (in address 20
H
), latch the values from the edge counters when the asynchronous hold signal
HOLD2
is set to low.
An initial value is given to the edge counter 1, EDGECNT1, by writing into the register SYEDGCNT1. An initial
value is given to the edge counter 2, EDGECNT2, by writing into the register SYEDGCNT2; see Table 1−18.
Table 1−18. Synchronous Latched Edge Count Register
RW0
RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 RW0 R− R−
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Bit 15−2: D15−2: The 14 MSBs of the synchronous latched edge counters
Bit 1−0: D1−0: The 2 LSBs of the synchronous latched edge counters. The value is adjusted to the value of the CNTAx
and CNTBx by a write access to these registers or a reset condition.
CNTAx CNTBx EDGECNTx bit 1 EDGECNTx bit 0 Position of the Angle
0 0 0 0 1st Quadrant
1 0 0 1 2nd Quadrant
1 1 1 0 3rd Quadrant
0 1 1 1 4th Quadrant
The data can only be read from the asynchronous latched registers ASEDGCNT1 and ASEDGCNT2; see
Table 1−19.
Table 1−19. Asynchronous Latched Edge Count Register
R0
R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Bit 15−0: D15−0: The 16 bits of the asynchronous latched edge counters
3.6.8 Edge Period Register (1E
H
and 22
H
)
There are two read-only shadow registers for the two edge-period registers. The registers SYEDGPRD1 and
SYEDGPRD2, synchronous edge period 1 (in address 1E
H
) and synchronous edge period 2 (in address 22
H
),
latch the values from the edge period registers when the synchronous hold signal HOLD1
is set to low. The
Edge Period Register is described in Table 1−20.
Table 1−20. Edge Period Register
R0
R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Bit 15−0: D15−0: The 16 bits of the synchronous latched edge period registers