Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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42
3.6.6 Counter Control/Status Register (1B
H
)
The Counter Control/Status Register is located in address 1
BH
. The counter control/status register
CCTRLSTAT is a combined control register for the filtered input of the counters and a status register for the
over- or under-flow status of the counters and the filtered input signals strobed by HOLD1
. See the Digital
Counters section for more information on this topic.
When the filter bits FxxE are set, the appropriate input is synchronized with the system clock and a digital filter
processes the input signal. If the bit is reset, the signals are just synchronized.
The overflow states EOx/TOx are set when the appropriate counter has reached the value FFFF
H
. This
indicates when the time, between two edges of the input signals, is greater than 4ms at 16MHz. Only the time
counter keeps its value until a counter reset is performed. See the Reset Register section for additional
information.
The filtered values of the counter inputs CNTA2, CNTA1, CNTB2 and CNTB1 are sampled with the
synchronous signal HOLD1
and are stored in the appropriate bits FB1, FA1, FB2 and FA2. The format of the
Counter Control/Status Register is described in Table 1−17.
Table 1−17. Counter Control/Status Register
R0
R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 RW1 RW1 RW1 RW1
FA1 FB1 FA2 FB2 0 0 0 0 EO2 TO2 EO1 TO1 FA2E FB2E FA1E FB1E
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Bit 15: FA1: Synchronously strobed FILTA1 signal
Bit 14: FB1: Synchronously strobed FILTB1 signal
Bit 13: FA2: Synchronously strobed FILTA2 signal
Bit 12: FB2: Synchronously strobed FILTB2 signal
Bit 7: EO2: EDGECNT2, over- or under-flow state
1 = when EDGECNT1 reached FFFF
H
0 = when EDGECNT1 is other than FFFF
H
Bit 6: TO2: TIMECOUNT2, over- or under-flow state
1 = when TIMECOUNT1 reached FFFF
H
0 = when TIMECOUNT1 is other than FFFF
H
Bit 5: EO1: EDGECNT1, over- or under-flow state
1 = when EDGECNT0 reached FFFF
H
0 = when EDGECNT0 is other than FFFF
H
Bit 4: TO1: TIMECOUNT1, over- or under-flow state
1 = when TIMECOUNT0 reached FFFF
H
0 = when TIMECOUNT0 is other than FFFF
H
Bit 3: FA2E: Enable of digital filter input CNTA2
1 = Input signal of CNTA2 will be filtered
0 = Input signal of CNTA2 will not be filtered
Bit 2: FB2E: Enable of digital filter input CNTB2
1 = Input signal of CNTB2 will be filtered
0 = Input signal of CNTB2 will not be filtered
Bit 1: FA1E: Enable of digital filter input CNTA1
1 = Input signal of CNTA1 will be filtered
0 = Input signal of CNTA1 will not be filtered
Bit 0: FB1E: Enable of digital filter input CNTB1
1 = Input signal of CNTB1 will be filtered
0 = Input signal of CNTB1 will not be filtered