Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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41
3.6.5 Control Register (1A
H
)
The Control Register is located in address 1A
H
. The control register contains the input selection and the DAV pin
control. (See the FIFO section for additional information.) The format of the Control Register is shown in Table 1−16.
For more about the input selection, see the Vecana Interface section.
Table 1−16. Control Registers
R0
R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 RW0 R0 RW0 RW0 RW0
0 0 0 0 0 0 0 0 0 0 0 DAV 0 I2 I1 I0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Bit 15−5, 3: Unused (read as ‘0’); don’t care at write
Bit 4: DAV: The 8 bits input to Digital-to-Analog Converter
1 = DAV signal active HIGH
0 = DAV signal active LOW
Bit 2−0: I2−0: Input channel selection bits
000 = AN3 for ADC
3
001 = AX for ADC
1
, BX for ADC
2
, and AN3 for ADC3
010 = A2 via SH
1
for ADC
1
, B2 via SH
3
for ADC
2
and AN2 for ADC
3
011 = A2 via SH
2
for ADC
1
, B2 via SH
4
for ADC
2
and AN2 for ADC
3
100, 101, 110 = A1 for ADC
1
, B1 for ADC
2
and AN1 for ADC
3
111 = IU for ADC
1
, IV for ADC
2
and IW for ADC
3