Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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3.6 Register Descriptions
The following table shows the symbols that are used in this section. The last number in the symbol represents
the reset value.
R Readable Bit
W Writeable Bit
U Unused
0/1 Value After Reset
The clock has to be running when the registers in the register map are accessed.
3.6.1 FIFO Data Register (00
H
)
The FIFO Data Register is at address 00
H
in the register map. The output word of the FIFO is in16-bit format.
The resolution of the ADCs is 12 bits. Output data from each of the ADCs is in binary two’s complement format.
The four MSBs are used for channel identification. The format of the output word is shown in Table 1−12.
There are three words stored in the FIFO for each conversion. There must be three read accesses to this
register to get all three conversion values out of the FIFO.
Table 1−12. FIFO Output Word Format
R0
R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0
CA3 CA2 CA1 CA0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
CA3−0: INPUT CHANNEL ADDRESS BITS
Bit 15−12: 0000 = Data from IU input
0001 = Data from A1 input
0010 = Data from A2 input
0011 = Data from IV input
0100 = Data from B1 input
0101 = Data from B2 input
0110 = Data from IW input
0111 = Data from AN1 input
1000 = Data from AN2 input
1001 = Data from AN3 input
1010 = Data from AX input
1011 = Data from BX input
1100 = Unused
1101 = Unused
1110 = Unused
1111 = Unused
Bit 11−0: DATA11−0: The output from the ADCs
In test mode, the upper four bits are copied from Bit 11 of the written data; see the FIFO Test Register (24
H
)
section.