Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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38
Table 1−11. Register Map Read 16-bit Data
ADDRESS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
00
H
FIFO data
01
H
Channel IU, read 10-bit offset DAC-value
(1)
02
H
Channel A1, read 10-bit offset DAC-value
(1)
03
H
Channel A2, read 10-bit offset DAC-value
(1)
04
H
Channel IV, read 10-bit offset DAC-value
(1)
05
H
Channel B1, read 10-bit offset DAC-value
(1)
06
H
Channel B2, read 10-bit offset DAC-value
(1)
07
H
Channel IW, read 10-bit offset DAC-value
(1)
08
H
Channel AN1, read 10-bit offset DAC-value
(1)
09
H
Channel AN2, read 10-bit offset DAC-value
(1)
0A
H
Channel AN3, read 10-bit offset DAC-value
(1)
0B
H
Channel AX, read 10−bit offset DAC−value
(1)
0C
H
Channel BX, read 10-bit offset DAC-value
(1)
0D
H
0 0 0 0 Channel IU, read 12-bit gain DAC-value
0E
H
0 0 0 0 Channel A1, read 12-bit gain DAC-value
0F
H
0 0 0 0 Channel A2, read 12-bit gain DAC-value
10
H
0 0 0 0 Channel IV, read 12-bit gain DAC-value
11
H
0 0 0 0 Channel B1, read 12-bit gain DAC-value
12
H
0 0 0 0 Channel B2, read 12-bit gain DAC-value
13
H
0 0 0 0 Channel IW, read 12-bit gain DAC-value
14
H
0 0 0 0 Channel AN1, read 12-bit gain DAC-value
15
H
0 0 0 0 Channel AN2, read 12-bit gain DAC-value
16
H
0 0 0 0 Channel AN3, read 12-bit gain DAC-value
17
H
0 0 0 0 Channel AX, read 12-bit gain DAC-value
18
H
0 0 0 0 Channel BX, read 12-bit gain DAC-value
19
H
(3) (3) (3) (3) (3) (3) (3) (3)
Over current, read 8-bit window DAC-value
1A
H
0 0 0 0 0 0 0 0 0 0 0 DAV 0 INPUT
1B
H
Read counter control and status register
1C
H
Counter 1, read 16-bit value in ASEDGCNT1 register
1D
H
Counter 1, read 16-bit value in SYEDGCNT1 register
1E
H
Counter 1, read 16-bit value in SYEDGPRD1 register
1F
H
Counter 1, read 16-bit value in SYEDGTIME1 register
20
H
Counter 2, read 16-bit value in ASEDGCNT2 register
21
H
Counter 2, read 16-bit value in SYEDGCNT2 register
22
H
Counter 2, read 16-bit value in SYEDGPRD2 register
23
H
Counter 2, read 16-bit value in SYEDGTIME2 register
24
H
Read 16-bit value in FIFO_TEST register
25
H
(2)
Read 6 MSB of COMP register B2 B1 A2 A1 UC VC WC UI VI WI
26
H
Read INTERRUPT register
27
H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARALLEL
28
H
Read 0000
H
29
H
−3F
H
Unused (read 0000
H
)
(1) MSB is copied to upper bits to achieve 16-bit two’s complement values.
(2) The lower 10 bits are the comparator outputs.
(3) The MSB of the 8-bit DAC is copied in the upper 8 bits.