Datasheet

! "  #$%  & &! 
&' &()    *"&&+ *,$-+ *,$ 
&./01
SBAS253E − MAY 2003 − REVISED JULY 2006
www.ti.com
35
3.4.4 Mode 11 Bus Access
(TMS320c54xx DSP Family-Compatible Mode)
In the TMS320c54xx DSP family-compatible mode (M1 = 1 and M0 = 1), the host port uses CS (pin 57)
together with WR
(pin 57) as an R/W for independent read and write access to the ADS7869. Bit 0 of the
PARALLEL register (address 27
H
) must have a value of 0 to use this compatible mode.
In this mode, CS
, together with the R/W (which remains high), indicates to the ADS7869 that the host
processor has requested a read data transfer (see Figure 1−18). The ADS7869 will output data to the host
as long as the CS
is an active low.
To configure the registers, in the ADS7869 the host puts the R/W
signal to low to indicate that valid data is
available on the bus. With the rising edge of the CS
, the data is latched into the ADS7869 (see Figure 1−19).
The address for the ADS7869 must be valid before the CS
is set to low.
Before using this mode, the register bit 0 at address 27
H
must be reset. The reset can be performed with a
TMS320C54xx DSP write operation with the original mode 11, because the write access is similar to the write
access of mode 11. (See Mode 11 Bus Access [standard mode] section.) This mode can perform read
operations, after bit 0 is reset, as mentioned above.
3.4.4.1 Read Timing Characteristics
(1)
Over recommended operating free-air temperature range at –40_C to +85_C, AV
DD
= 5V, BV
DD
= 3V − 5V.
PARAMETER
SYMBOL MIN MAX UNIT
Delay time from CS LOW to output data not in tri-state mode t
D1
8 ns
Access time from address valid to output data valid t
A1
10 ns
Delay time from address not valid to output data not valid
(2)
t
D2
0 8 ns
Delay time from CS HIGH to output data in tri-state mode t
D3
8 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of BV
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) One or more read cycles can be performed in one CS
cycle.
CS
t
A1
t
D1
t
D2
t
D3
t
A1
R/W
D(15:0)
A(5:0)
Figure 1−18. Mode 11 Read Access (TMS320c54xx mode)