Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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33
3.4.3 Mode 11 Bus Access
(Standard Mode)
When M1 = 1 and M0 = 1 (mode 11), the host port uses WR (pin 58) and RD (pin 59) for independent write
and read access to the ADS7869. The current cycle is processed only when the CS
(pin 57) input of the
ADS7869 is an active low. Bit 0 of the PARALLEL register (Address 27
H
) must have a reset value of 1 to use
the standard mode.
In Mode 11 operation, RD
indicates to the ADS7869 that the host processor has requested a data transfer
(see Figure 1−16). The ADS7869 outputs data to the host. The address can be changed within a CS
low cycle,
and more than one data can be read.
To configure the registers in the ADS7869, the host issues a WR
signal to indicate that valid data is available
on the bus. With the rising edge of the WR
the data is latched into the ADS7869; see Figure 1−17. The address
for the ADS7869 must be valid before the write operation takes place. The CS
signal can stay low between
two consecutive writes.
3.4.3.1 Read Timing Characteristics
(1)
Over recommended operating free-air temperature range at –40_C to +85_C, AV
DD
= 5V, BV
DD
= 3V − 5V.
PARAMETER
SYMBOL MIN MAX UNIT
Delay time from CS LOW to output data not in tri-state mode
(2)
t
D1
8 ns
Access time from address valid to output data valid t
A1
10 ns
Delay time from address not valid to output data not valid
(3)
t
D2
0 8 ns
Delay time from CS HIGH to output data in tri-state mode
(4)
t
D3
8 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of BV
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) Refer to CS
signal or RD signal whichever occurs last.
(3) One or more read cycles can be performed in one CS
cycle.
(4) Refer to CS
signal or RD signal whichever occurs first.
CS
t
A1
t
D1
t
D2
t
D3
t
A1
RD
WR
D(15:0)
A(5:0)
Figure 1−16. Mode 11 Read Access (Standard Mode)