Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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31
3.4.2 Mode 10 Bus Access
When M1 = 1 and M0 = 0 (mode 10), the host port uses the RD (pin 59) as a read/write signal (R/W) and the
WR
(pin 58) as a write-enable signal WE. The current cycle is only processed when the chip select input CS
(pin 57) of the ADS7869 is active low.
R/W
determines the direction of the transfer during a bus cycle; see Figure 1−14. When R/W is high, data is
placed on the databus by ADS7869, according to the address, as long as CS
is low.
For a write cycle, a low-level signal (on WE
) indicates to the ADS7869 that the data on the bus is valid. With
the rising edge of WE
the data is latched into the ADS7869. When the host sets CS to low, a valid access to
the ADS7869 is detected (see Figure 1−15).
3.4.2.1 Read Timing Characteristics
(1)
Over recommended operating free-air temperature range at –40_C to +85_C, AV
DD
= 5V, BV
DD
= 3V − 5V.
PARAMETER
SYMBOL MIN MAX UNIT
Delay time from CS LOW to output data not in tri-state mode
(2)
t
D1
8 ns
Access time from address valid to output data valid t
A1
10 ns
Delay time from address not valid to output data not valid
(3)
t
D2
0 8 ns
Delay time from CS HIGH to output data in tri-state mode
(4)
t
D3
8 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of BV
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) Refer to CS
signal or R/W signal whichever occurs last.
(3) One or more read cycles can be performed in one CS
cycle.
(4) Refer to CS
signal or R/W signal whichever occurs first.
CS
t
A1
t
D1
t
D2
t
D2
t
A1
R/W
WE
D(15:0)
A(5:0)
Figure 1−14. Mode 10 Read Access