Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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3.4 Parallel Interface
The Parallel Interface has the following major capabilities:
1. Data words:
• Data path with a width of 16 bits is supported.
2. Bus handshaking:
• Separate RD
and WR style control signals.
• Separate R/W
and WE style control signals.
3. Mapping
• The ADS7869 appears as a memory-mapped peripheral. See Table 1−10 on page 37 and Table 1−11 on
page 38.
• Internal registers are directly mapped into consecutive locations in the external bus address space.
3.4.1 Parallel Read and Write Control
Reading from and writing to the ADS7869 is controlled by the chip select input (CS, pin 57), the write input
(WR
, pin 58) and the read input (RD, pin 59). There is a control bit for mode 11, which can be reset to activate
a special compatibility mode. (See Mode 11 Bus Access [DSP-compatible mode] section.) The read and write
pins can be configured as a combined Read/Write and Write enable depending on the needs of the host
processor. The mode pins M0 and M1 determine the method by which the ADS7869 is accessed by the host
(see Table 1−9).
Table 1−9. Host Parallel Port Operation
[M1, M0] PIN NAME PIN NO. FUNCTION OPERATION
,10‘
R/W 59 Read/Write Signal
0: Data can be written to ADS7869; see WE
1: Data from ADS7869 is written to the Data Bus
,10‘
WE 58 Write Enable
0: Data Bus is read by ADS7869 at rising edge
1: ADS7869 Write function is disabled
,11‘
standard
RD 59 Read Signal 0: Data from ADS7869 is written to the Data Bus
1: ADS7869 Read function is disabled
,11‘
standard
WR 58 Write Signal 0: Data Bus is read by ADS7869 at rising edge
1: ADS7869 Write function is disabled
,11‘
— 59 — Signal is ignored by ADS7869
,11‘
TMS
R/W 58 Read/Write Signal
0: Data Bus is read by ADS7869 at rising edge of CS
1: Data from ADS7869 is written to the Data Bus