Datasheet

! "  #$%  & &! 
&' &()    *"&&+ *,$-+ *,$ 
&./01
SBAS253E − MAY 2003 − REVISED JULY 2006
www.ti.com
28
One 16-bit transfer is accomplished, as follows:
1. On the first falling edge of SPICLK, the read/write bit is strobed.
2. On the third falling edge of SPICLK, the MSB of the address (bit 5) is strobed.
3.
On the eighth falling edge of SPICLK, the LSB of the address (bit 0) is strobed and the corresponding data of the register
map is read.
4. On the ninth rising edge, the data read from the register map is latched into a shift register and shifted one position
each rising edge of the SPICLK. This data is always sent out, even when a write operation is performed.
5. On the 24th falling edge of SPICLK, the last data bit is shifted in from SPISIMO and a write pulse is generated to write
the data into the register map, if a write operation was performed.
During continuous read or write (see Figure 1−12), the address is decrementing after each read or write; see
the indicating arrows. When the address is set to 00
H
, in the beginning, the FIFO can be read out fast. The
data is written into the register map on the 16th SPICLK of a data word. If the SPISTE
is inactive before the
16th SPICLK in a data word, the data is not written into the register map; therefore, the data is lost.
SPISTE
SPICLK 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs
SPISIMO Address 1st Data to Write 2nd Data to Write 3rd Data to Write 4th Data to Write
Don’t Care 1st Read Data 2nd Read Data 3rd Read Data 4th Read DataSPISOMI
Figure 1−12. Continuous SPI Transfer Cycle