Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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3.2.3 WINCLK Selection
It is possible to apply a separate clock for the window comparators at the WINCLK (pin 51) in VECANA01
mode. By using the pins S0 (pin 52) and S1 (pin 53) as decoder inputs, the window comparators can be
supplied with the system clock, an external clock (supplied by the WINCLK), and two divided external clocks;
see Table 1−7.
Table 1−7. Window Comparator Clock
S1 S0 Clock to Window Comparators
0 0 Synchronous system clock
0 1 External WINCLK clock
1 0 External WINCLK clock / 2
1 1 External WINCLK clock / 4
The system clock, provided by CLK (pin 77), drives the window comparators in the other modes (SPI and
parallel modes).
The window comparator clock, WINCLK, must be synchronous with the system clock, provided by CLK (pin
77). The window comparators can be supplied with a 6MHz clock when the system runs with a 15MHz clock.
In order to provide the window comparators with a maximum of 1µs detection time, a minimum clock of 6MHz
must be supplied. See the Window Comparator section. It is necessary to operate the window comparators
with a continuous clock.
3.3 Serial Peripheral Interface (SPI)
The SPI runs fully asynchronous to the rest of the system. The four signals of the SPI are SPICLK, SPISIMO,
SPISOMI and SPISTE
. The maximum speed of the SPI is 25MHz. When the select signal SPISTE is HIGH,
the entire SPI, except the address and the data registers, is in reset state. The SPI clock SPICLK and the serial
data input SPISIMO are disabled when SPISTE
is HIGH. The incoming data is strobed by the SPI on the falling
edge of the SPICLK. Outgoing data is put on the output SPISOMI on the rising edge of the SPICLK (see
Figure 1−11). For a transmission of one 16-bit data word, 24 bits are required. The first incoming bit to the
ADS7869 determines if the whole transmission is a read or a write operation. A ‘1’ means a read and a ‘0’
means a write operation. There are seven address bits, but only the six LSBs are used. Then the 16 data bits
are transmitted or received (see Table 1−8).
SPISTE
1
SPICLK
SPISIMO
SPISOMI
2 3 4 5
Figure 1−11. One SPI Transfer Cycle
Table 1−8. SPI Write 24-bit Word Format
A23
A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
R/W X Address Data