Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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26
Input Select = 7
H
IU is sampled by the synchronous sample-and-hold, SH
1
; ADC
1
converts it on the signal HOLD1. IV is
sampled by the synchronous sample-and-hold, SH
3
; ADC
2
converts it on the signal HOLD1. IW is sampled
by the synchronous sample-and-hold, SH
5
; ADC
3
converts it on the signal HOLD1.
3.2.2 VECANA Timing Characteristics
(1)
Over recommended operating free-air temperature range at –40_C to +85_C, AV
DD
= 5V, BV
DD
= 3V − 5V.
PARAMETER
SYMBOL MIN MAX UNIT
ADCLK Period t
C1
62.5 ns
ADCLK HIGH or LOW Time t
W1
20 ns
HOLD1 Signal Setup Time t
SU1
25 ns
HOLD1 Signal Hold Time t
H1
20 15 + 12.5t
C1
ns
HOLD2 Signal Setup Time t
SU2
0 ns
HOLD2 Signal Hold Time t
H2
0 ns
Delay Time from ADCLK Rising to DAV Falling Edge t
D1
15 ns
Output Data Delay Time t
D2
10 ns
Input Data Setup Time t
SU3
10 ns
Input Data Hold Time t
H3
10 ns
Delay Time from ADCLK Rising to DAV Rising Edge t
D3
15 ns
Sampling Time t
SAMPLE
4 t
C1
(1) All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of BV
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
CLK
HOLD1
1 2 3 4 12 13 14 1 2
t
C1
t
W1
t
H1
t
SAMPLE
t
H2
t
D3
t
D4
t
SU1
t
SU2
t
D1
t
SU3
t
H3
t
D2
Data OUT
D11 (MSB)
D10 D1
Data OUT
D0 (LSB)
Data OUT
D11 (MSB)
Data OUT
D11 (MSB)
D10 D1
Data OUT
D0 (LSB)
Data OUT
D11 (MSB)
Data OUT
D11 (MSB)
D10 D1
Data OUT
D0 (LSB)
Data OUT
D11 (MSB)
Data IN
D12 (MSB)
D11 D10
D1
Data IN
D0 (LSB)
Data IN
D12 (LSB)
HOLD2
DAV
ADOUT1
ADOUT2
ADOUT3
ADIN
Figure 1−10. VECANA Access