Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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3.2 VECANA Interface
The VECANA01 mode of the ADS7869 interface acts exactly like the original VECANA01 interface. This mode
was added to the ADS7869 for backward-compatibility purposes. The VECANA01 interface is a proprietary
serial interface with one serial input and three serial outputs.
Sampling and conversion are controlled with the HOLD1
and CLK inputs. The ADS7869 is designed to
operate with an external clock supplied to the CLK input. This allows the conversion to be synchronous with
the system clock, thus reducing transient noise effects. The DAV signal indicates when a conversion is taking
place with a low-level pulse. The DAV signal is equivalent to the ADBUSY signal in the VECANA01.
The typical clock frequency for the specified accuracy is 16MHz. This results in a complete conversion cycle,
S/H acquisition and analog-to-digital (A/D) conversion of 1µs. It is possible to stop the clock after 14 clock
cycles and start it again when the next conversion starts (after HOLD1
goes low); see the WINCLK Selection
section.
When power is applied to the ADS7869, one conversion cycle is required for initialization before valid digital
data is transmitted on the second cycle. The first conversion after power is applied is performed with
indeterminate configuration values in the Input Setup Register. The second conversion uses those values to
perform proper conversions and to output valid digital data from each of the ADCs.
The setup word received by the ADS7869 is used for the next conversion cycle while the ADCs are converting
and transmitting their serial digital data for one conversion cycle. The 13-bit word is supplied to ADIN (pin 67),
and is stored in the buffered Input Setup Register.
Configuration parameters are:
• DAC output voltage;
• Programmable gain/input voltage range;
• Input multiplexer; and
• sample-and-hold selection.
The DAC Input portion of the ADIN word (bits DAC [7...0]) determines the value of the DAC output voltage;
see Table 1−5. The 8-bit DAC has 256 possible output steps from 0V to +2.490V. The value of 1LSB is 9.76mV
(see Table 1−3 for input/output relationships).
Table 1−3 to Table 1−6 show information regarding these parameters.
Table 1−3. DAC Input/Output Relationships
DAC Input Code Analog Output
00
H
0000 0000
B
0V
01
H
0000 0001
B
+0.010V
... ... ...
... ... ...
FF
H
1111 1111
B
+2.490V
Table 1−4. VECANA Gain Select Information
Gain Select Bits Gain Setting Input Voltage Range
0
H
5.0V/V ±0.5V
1
H
2.5V/V ±1.0V
2
H
1.25V/V ±2.0V
3
H
1.0V/V ±2.5V