Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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18
2.2.2 Clock
The ADC uses the external clock CLK, which needs to be in the range of 1MHz to 16MHz. 12 clock cycles
are necessary for a conversion, with a minimum of four clock cycles for the acquisition. Therefore, the
maximum throughput rate of 1MSPS is achieved with a 16MHz clock and 16 clock cycles per complete
conversion cycle. The duty cycle should be 50%; however, the ADS7869 will still function properly with a duty
cycle between 30% and 70%.
2.2.3 Reset
A reset condition stops any ongoing conversion and reconnects the synchronous S/Hs to the inputs; see the
Reset Section.
2.2.4 Gain Adjustment
The output of a 12-bit DAC (REF_ADC) is used as the reference voltage for the ADC. There is one DAC for
each ADC. The voltage range is between 0V (code 000
H
) and the 2.5V of REFIN (code FFF
H
). The ADC
operates correctly if the selected voltage is in the range of 0.5V to 2.5V. The output voltage of the DAC sets
the differential input range of the ADC, which is ±REF_ADC. The desired input range can be adjusted in
1.22mV steps.
In the VECANA mode, the gain information contained in the digital input word ADIN automatically sets the
DAC value. See the Vecana Interface section for further information.
In all other modes, there is a register for every input channel inside the digital interface, which stores the gain
information for any given channel. When a particular channel is selected by the application, the value of this
register is automatically written to the DAC and the DAC output is adjusted to the desired value. The DAC
settles to this value within 250ns (equivalent to the minimum acquisition time).
The gain information inside the registers is set to zero when a reset condition occurs. These registers need
to be set to the selected value before the ADCs are used.
In VECANA mode, the DAC is initially set to Full-Scale and the differential input range is equal to ±(voltage
at the REFIN pin).
CAUTION: An essential offset error occurs when data is held on the sampling capacitors A2 and B2 (or
AX and BX) and the gain of the ADC is modified in intermediate conversions before converting the
particular channels A2 and B2 (or AX and BX). This offset error is possible under two conditions:
1. Data can be held on the asynchronous sample-and-hold capacitors AX and BX with the HOLD2
signal.
Other channels can be converted before the asynchronous signals AX and BX. The offset error occurs
if the gain is changed during these conversions.
2. With the input commands 4−6, channels A1 and B1 are held together with A2 and B2. Channels A1 and
B1 will be converted first. During this conversion or further intermediate conversions, the offset error
occurs if the gain is modified before the conversion of channels A2 and B2.
2.2.5 Offset Adjustment
The offset can be adjusted, similar to the gain, to a 12-bit level with respect to the actual input voltage range
of the ADC. For example, if the input range is ±1V, the offset can be adjusted in increments of 488µV. The
maximum adjustment is ±12.5% of the input range.
There is a register inside the digital interface for each input channel. This registers store the offset adjustment
value for each channel. When a channel is selected for conversion, the offset is automatically adjusted. The
selected channel and the related register information must not be changed during the conversion.
Setting the register to 201
H
results in a –12.5% adjustment, 000
H
results in no adjustment, and 1FF
H
results
in a +12.5% adjustment. The offset adjustment value 200
H
is not allowed.
The offset adjustment cannot be used in VECANA mode. A reset condition will set the offset adjustment to
zero.