Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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17
2.1.2 Window Comparator Inputs
A sampling architecture was selected for the window comparators. The sampling time is two clock cycles with
a minimum t
AQ
(see Equation 1) of 125ns. The necessary accuracy is 10mV (see 8-bit DAC section) with a
5V input range. The required bandwidth of the driving amplifier is 8.8MHz (see Equation 1). The OPAx354
from Texas Instruments is recommended.
The input circuit of the window comparator is similar to the ADC inputs. The only difference is that the sampling
capacitors are reduced to 2.5pF. (See Figure 1−4.)
R
SER
300
Ω
R
SW
80
Ω
C
PAR
5pF
C
S
2.5pF
R
SER
300
Ω
R
SW
80
Ω
C
PAR
5pF
C
S
2.5pF
IN+
IN
−
Figure 1−4. Equivalent Input Circuit of the Window Comparators
2.1.3 Sign Comparator Inputs
Four sign comparators are connected to the ADC inputs (A1, B1, A2 and B2); three of the sign comparators
are wired to the window comparator inputs (U_C, V_C, and W_C).
The sample capacitors of the ADCs and the window comparators could produce voltage glitches; therefore,
it is important to drive the inputs with low impedance.
The lower voltage of the differential input should remain within the range of 0 to AV
DD
−1.8V.
2.2 Analog-To-Digital Converter
The ADS7869 includes three, SAR-type, 1MSPS, 12-bit ADCs, and three pairs of S/H capacitors, which are
each connected to ADC
1
and ADC
2
. A single S/H capacitor is connected to ADC
3
. Gain and offset adjustments
are added to each ADC. (See Figure 1−2 on page 15.)
2.2.1 HOLD1, HOLD2
The analog inputs are held when the HOLDx signals go low. The charges of the synchronous
sample-and-holds (S/H
1−5
) are frozen on the falling edge of HOLD1. The setup time of HOLD1, against the
rising edge of the system clock, is typically 25ns. The conversion will automatically start on the next rising edge
of the clock. The S/Hs are switched back into the sample mode when the conversion is finished, 12 clock
cycles later. This point of time is indicated by DAV. (See Figure 1−10 on page 26.) HOLD1
must go high at
the latest at the 13th falling clock after conversion start.
The asynchronous sample and holds (S/H
6−7
) are triggered by the active low HOLD2 signal. The setup time
of HOLD2
, against the falling edge of HOLD1, is 0ns; see Figure 1−10. The conversion of these S/H circuits
is initiated when they are selected through the digital interface and the HOLD1
signal goes low. The inputs
are connected back to the S/H capacitor when the HOLD2
signal goes high. HOLD2 needs to be low during
the whole conversion. It is possible to connect HOLD1
and HOLD2 together.