Datasheet

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SBAS253E − MAY 2003 − REVISED JULY 2006
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16
2 Analog Section
The analog section addresses the Analog-to-Digital Converters, including the gain and offset adjustment.
There is also a discussion of the analog inputs, the seven sign comparators, three window comparators, the
8-bit Digital-to-Analog Converter (DAC), the reference voltage, grounding, and the supply voltage.
2.1 Fully Differential Analog Inputs
2.1.1 Analog-to-Digital Converter Inputs
The 12 inputs to the ADCs, as well as the three inputs (U_C, V_C and W_C) to the comparators, are fully
differential and provide a good common-mode rejection of 60dB at 50kHz. This is very important to suppress
noise in difficult environments.
The seven sample-and-hold circuits from the ADC contain a 5pF capacitor (C
s
in Figure 1−3) that is connected
via a switch to the analog inputs. Opening the switch holds the data. The switch closes when the conversion
is finished. The capacitor is then loaded to an initial voltage that is equal to the reference at the ADC, which
is selected with the gain adjustment.
The voltage of the input pin is usually different from the voltage of the sample capacitor when the input switch
closes. The sample capacitor needs to be recharged to the 12-bit accuracy, one-half of a least significant bit
(LSB), within an acquisition time (t
AQ
) of at least 200ns.
The minimum −3dB bandwidth of the driving operational amplifier can be calculated to:
f
3db
+
ln(2) @ (n ) 1)
2p @ t
AQ
where n is equal to 12, the resolution of the ADC (in the case of the ADS7869). When t
AQ
= 200ns, the minimum
bandwidth of the driving amplifier is 7MHz. The bandwidth can be relaxed if the acquisition time is increased
by the application.
The OPA364 from Texas Instruments is recommended; besides the necessary bandwidth, it provides a low
offset in a small package at a low price.
The phase margin of the driving operational amplifier is usually reduced by the sampling capacitor of the ADC.
A resistor between the capacitor and the amplifier reduces this effect; therefore, an internal 300Ω resistor
(R
SER
) is in series with the switch. The resistance of the closed switch (R
SW
) is approximately 80Ω. See
Figure 1−3.
R
SER
300
Ω
R
SW
80
Ω
C
PAR
5pF
C
S
5pF
R
SER
300
Ω
R
SW
80
Ω
C
PAR
5pF
C
S
5pF
IN+
IN
−
Figure 1−3. Equivalent Input Circuit to the ADCs
The differential input range (positive minus negative input) of the ADC is ±REF_ADC, the reference of the
converter, which is selected with the gain adjustment.
It is important that the voltage to all inputs does not exceed more than 0.3V above the analog supply or 0.3V
below the ground. There is no DC current flow through the inputs. Current is only necessary when recharging
the sample-and-hold capacitors, C
S
.
(1)