ADS7869 Analog Motor Control Front-End with Simultaneous Sampling on Seven S/H Capacitors and Three 1MSPS, 12-Bit, 12-Channel ADCs Data Manual Literature Number: SBAS253E May 2003 − Revised July 2006 ! !
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! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3 vi Digital Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 List of Illustrations 1−1. Typical Motor Control Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2. Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 List of Tables 1−1. Selection of Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2. Mode vs Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 1.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 1.5 ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range at –40_C to +85_C, AVDD = 5V, BVDD = 3.3V, VREF = internal +2.5V, fCLK = 16MHz, fSAMPLE = 1 MSPS, unless otherwise noted.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 1.5 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating free-air temperature range at –40_C to +85_C, AVDD = 5V, BVDD = 3.3V, VREF = internal +2.5V, fCLK = 16MHz, fSAMPLE = 1 MSPS, unless otherwise noted.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 1.5 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating free-air temperature range at –40_C to +85_C, AVDD = 5V, BVDD = 3.3V, VREF = internal +2.5V, fCLK = 16MHz, fSAMPLE = 1 MSPS, unless otherwise noted.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 1.
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! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 Asynchronous Reset Mode Select +5V Analog Supply +5V Analog Supply Enco der Counter1 Inputs Asynchronous Hold BASIC CIRCUIT CONFIGURATION C onvert Start 1.8 +2.7V to +5.5V D igita l Supply 10 µ F + 10 µ F + 0.1 µ F 0.1 µ F 0.1 µ F 0.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 1.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 1.10 TYPICAL CHARACTERISTICS At TA = +25_C, AVDD = 5V, BVDD = 3.3V, VREF = internal +2.5V, fCLK = 16MHz, fSAMPLE = 1 MSPS, unless otherwise noted. REFERENCE VOLTAGE vs TEMPERATURE ANALOG SUPPLY CURRENT vs TEMPERATURE 2.500 50 2.498 Voltage (V) Current (mA) 48 46 44 2.494 2.492 42 40 2.496 2.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 TYPICAL CHARACTERISTICS (Continued) At TA = +25_C, AVDD = 5V, BVDD = 3.3V, VREF = internal +2.5V, fCLK = 16MHz, fSAMPLE = 1 MSPS, unless otherwise noted. ADC DIFFERENTIAL LINEARITY vs TEMPERATURE ADC DIFFERENTIAL LINEARITY ERROR vs CODE 1.0 1.0 Max 0.5 DNL (LSB) DNL (LSB) 0.5 0 −0.5 0 −0.5 Min −1.0 −40 25 −1.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 TYPICAL CHARACTERISTICS (Continued) At TA = +25_C, AVDD = 5V, BVDD = 3.3V, VREF = internal +2.5V, fCLK = 16MHz, fSAMPLE = 1 MSPS, unless otherwise noted. DAC GAIN ERROR vs TEMPERATURE 0 0.8 −0.05 −0.10 Gain Error (%) Offset Error (LSB) DAC OFFSET ERROR vs TEMPERATURE 1.0 0.6 0.4 −0.15 −0.20 0.2 0 −0.25 −0.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 TYPICAL CHARACTERISTICS (Continued) At TA = +25_C, AVDD = 5V, BVDD = 3.3V, VREF = internal +2.5V, fCLK = 16MHz, fSAMPLE = 1 MSPS, unless otherwise noted.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 1.11 FUNCTIONAL BLOCK DIAGRAM IUp IUn Offset A1p A1n A2p A2n Gain SH 1 DAC 1 12−Bit RAM DAC 2 12−Bit FIFO MUX 1 ADC 1 12−Bit SH 2 ADDR <0.5> Input Select MUX 4 Axp Axn SH 6 C onv IVp IVn Offset B1p B1n B2p B2n Gain SH 3 DAC 3 12−Bit DAC 4 12−Bit MUX 2 D ATA<0.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 2 Analog Section The analog section addresses the Analog-to-Digital Converters, including the gain and offset adjustment. There is also a discussion of the analog inputs, the seven sign comparators, three window comparators, the 8-bit Digital-to-Analog Converter (DAC), the reference voltage, grounding, and the supply voltage. 2.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 2.1.2 Window Comparator Inputs A sampling architecture was selected for the window comparators. The sampling time is two clock cycles with a minimum tAQ (see Equation 1) of 125ns. The necessary accuracy is 10mV (see 8-bit DAC section) with a 5V input range. The required bandwidth of the driving amplifier is 8.8MHz (see Equation 1).
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 2.2.2 Clock The ADC uses the external clock CLK, which needs to be in the range of 1MHz to 16MHz. 12 clock cycles are necessary for a conversion, with a minimum of four clock cycles for the acquisition. Therefore, the maximum throughput rate of 1MSPS is achieved with a 16MHz clock and 16 clock cycles per complete conversion cycle.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 2.2.6 Transition Noise The transition noise of the ADS7869 itself is low, as shown in Figure 1−5. Applying a low-noise DC input and initiating 8000 conversions generated this histogram. 10000 7986 Number of Occurrences 8000 6000 4000 2000 0 13 3030 3031 1 0 3033 3034 0 3032 Code (decimal) Figure 1−5.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 The input range of the comparators is limited. The lower voltage of the differential inputs should always be within the range of 0 to AVDD−1.8V. On every comparator, the output is delayed to the input voltage. This delay is dependent on the overdrive of the comparator inputs.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 2.4 Window Comparators The window comparators test if the input voltage is within a certain range; this range is ±(voltage applied to DAIN, pin 30). If the differential input voltage remains within this range, then the output of the window comparator is 1. If the voltage is outside this range, then the output is set to 0.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 2.5 8-Bit Digital-to-Analog Converter A voltage between 0.5V to 2.5V is required at DAIN (pin 30) to set the range of the window comparators; this can be accomplished with the 8-bit DAC. The DAC value is programmed via the digital interface. Input code 00H corresponds to a DAC output voltage of 0V.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3 Digital Section 3.1 Introduction The ADS7869 can interface with a DSP or µC in four different ways. The M1 and M0 pins determine in which mode the ADS7869 will communicate; see Table 1−1. It can be connected as a standard VECANA01 interface, as an SPI, or as two different parallel interfaces. Table 1−1.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.2 VECANA Interface The VECANA01 mode of the ADS7869 interface acts exactly like the original VECANA01 interface. This mode was added to the ADS7869 for backward-compatibility purposes. The VECANA01 interface is a proprietary serial interface with one serial input and three serial outputs.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 The Gain Select portion (bits GAIN [1..0]) determines the programmable gain of the ADIN word; see Table 1−5. The gain for all three ADCs is set by one gain input parameter. The gain values and allowable full-scale inputs are shown in Table 1−4.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 Input Select = 7H IU is sampled by the synchronous sample-and-hold, SH1; ADC1 converts it on the signal HOLD1. IV is sampled by the synchronous sample-and-hold, SH3; ADC2 converts it on the signal HOLD1. IW is sampled by the synchronous sample-and-hold, SH5; ADC3 converts it on the signal HOLD1. 3.2.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.2.3 WINCLK Selection It is possible to apply a separate clock for the window comparators at the WINCLK (pin 51) in VECANA01 mode.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 One 16-bit transfer is accomplished, as follows: 1. On the first falling edge of SPICLK, the read/write bit is strobed. 2. On the third falling edge of SPICLK, the MSB of the address (bit 5) is strobed. 3.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.3.1 SPI Timing Characteristics (1) Over recommended operating free-air temperature range at –40_C to +85_C, AVDD = 5V, BVDD = 3V − 5V.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.4 Parallel Interface The Parallel Interface has the following major capabilities: 1. Data words: • Data path with a width of 16 bits is supported. 2. Bus handshaking: • Separate RD and WR style control signals. • Separate R/W and WE style control signals. 3. Mapping • The ADS7869 appears as a memory-mapped peripheral.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.4.2 Mode 10 Bus Access When M1 = 1 and M0 = 0 (mode 10), the host port uses the RD (pin 59) as a read/write signal (R/W) and the WR (pin 58) as a write-enable signal WE. The current cycle is only processed when the chip select input CS (pin 57) of the ADS7869 is active low.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.4.2.2 Write Timing Characteristics(1) Over recommended operating free-air temperature range at –40_C to +85_C, AVDD = 5V, BVDD = 3V − 5V.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.4.3 Mode 11 Bus Access (Standard Mode) When M1 = 1 and M0 = 1 (mode 11), the host port uses WR (pin 58) and RD (pin 59) for independent write and read access to the ADS7869. The current cycle is processed only when the CS (pin 57) input of the ADS7869 is an active low.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.4.3.2 Write Timing Characteristics(1) Over recommended operating free-air temperature range at –40_C to +85_C, AVDD = 5V, BVDD = 3V − 5V.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.4.4 Mode 11 Bus Access (TMS320c54xx DSP Family-Compatible Mode) In the TMS320c54xx DSP family-compatible mode (M1 = 1 and M0 = 1), the host port uses CS (pin 57) together with WR (pin 57) as an R/W for independent read and write access to the ADS7869.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.4.4.2 Write Timing Characteristics(1) Over recommended operating free-air temperature range at –40_C to +85_C, AVDD = 5V, BVDD = 3V − 5V.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.5 Register Map Table 1−10.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 Table 1−11.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.6 Register Descriptions The following table shows the symbols that are used in this section. The last number in the symbol represents the reset value. R Readable Bit W Writeable Bit U Unused 0/1 Value After Reset The clock has to be running when the registers in the register map are accessed. 3.6.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.6.2 Offset Registers (01H to 0CH ) The Offset Registers are stored at the addresses 01H to 0CH. The Offset Registers are 10 bits wide and represented in the two’s complement format. The sign bit is copied in bit locations 15 to 10.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.6.5 Control Register (1AH ) The Control Register is located in address 1AH. The control register contains the input selection and the DAV pin control. (See the FIFO section for additional information.) The format of the Control Register is shown in Table 1−16. For more about the input selection, see the Vecana Interface section.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.6.6 Counter Control/Status Register (1BH ) The Counter Control/Status Register is located in address 1BH.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.6.7 Edge Count Register (1CH , 1DH , 20H and 21H ) There are four shadow registers for the two edge counters.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.6.9 Edge Time Period Register (1FH and 23H ) There are two read-only shadow registers for the two edge time counters.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.6.11 Comparator Test Register (25H ) The purpose of the Comparator Test Register, in address 25H, is to apply a defined pattern to the comparator output pins. This feature is for testing algorithms in the DSP or testing the hardware controlled by the comparator outputs.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.6.12 Interrupt Register (26H ) The Interrupt Register, in address 26H, contains the interrupt source and interrupt control bits. The bits xOxF are set when a particular counter had an over- or under-flow.
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! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.6.14 Reset Register (28H ) The Reset Register, in address 28H, can either reset the ADS7869 entirely, or simply reset the counters. Writing an AAH pattern to the CX bits will reset both counter 1 and counter 2, and all registers related to the counters.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.7 FIFO The FIFO of the ADS7869 is organized as a 32-word ring buffer with 16 bits per word, shown in Figure 1−20. 30 31 32 1 2 3 4 29 28 5 Read Pointer 6 27 7 26 25 8 24 9 23 10 22 11 21 Data in FIFO 12 20 13 19 18 17 16 15 14 Free Write Pointer Figure 1−20.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 The DAV signal becomes active when the write pointer is ahead of the read pointer. The DAV signal becomes inactive again when the read pointer equals the write pointer (that is, when the FIFO is empty).
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 DAV Timing Characteristics(1) 3.7.1 Over recommended operating free-air temperature range at –40_C to +85_C, AVDD = 5V, BVDD = 3V − 5V.
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! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.8.2 Digital Noise Filter A digital noise filter rejects noise on the incoming quadrature signal. The digital noise filter rejects large, short duration, noise spikes; false counts, triggered by noise or spikes, are also significantly suppressed. See Figure 1−24.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 Filtered Timing Characteristics(1) 3.8.2.1 Over recommended operating free-air temperature range at –40_C to +85_C, AVDD = 5V, BVDD = 3V − 5V. PARAMETER SYMBOL MIN CLK Period tC1 62.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 Unfiltered Timing Characteristics(1) 3.8.2.2 Over recommended operating free-air temperature range at –40_C to +85_C, AVDD = 5V, BVDD = 3V − 5V. PARAMETER SYMBOL MIN CLK Period tC1 62.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.8.3 Binary Counters and Registers The complete up/down counter includes two 16-bit counters and five 16-bit shadow registers. The first counter is a 16-bit up/down counter, which counts upwards or downwards on the EDGE input signal as a function of the U/D signal. This is the coarse angle counter, and it is called EDGECNT.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 When EDGECNT cause an over- or under-flow, the corresponding bit in the Interrupt Register is set. The counter continues to increment or decrement in value. When the EDGE signal rises, the TIMECOUNT value is latched into the shadow register EDGEPRD.
! " # $% & & ! & ' &() *"& &+ *,$- + *,$ &./01 www.ti.com SBAS253E − MAY 2003 − REVISED JULY 2006 3.9 Interrupt The interrupt can have several sources: • FIFO full status • FIFO empty status • Two TIMECOUNT over- or under-flows • Two EDGECOUNT over- or under-flows These six sources are combined into one interrupt signal.
Revision History DATE REV PAGE 7/06 E 2 SECTION Ordering Information DESCRIPTION Changed ordering number and transport media. NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 29-Oct-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS7869IPZTR Package Package Pins Type Drawing TQFP PZT 100 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 17.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 17.0 1.5 20.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 29-Oct-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7869IPZTR TQFP PZT 100 1000 346.0 346.0 41.
MECHANICAL DATA MTQF012B – OCTOBER 1994 – REVISED DECEMBER 1996 PZT (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 0,13 NOM 25 1 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 1,20 MAX 0,08 4073179 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
