Datasheet
www.ti.com
SPECIFICATIONS, ADS7867
ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
At –40 ° C to 85 ° C, f
SAMPLE
= 240 KSPS and f
SCLK
= 3.4 MHz if 1.6 V ≤ V
DD
≤ 3.6 V; f
SAMPLE
= 120 KSPS and f
SCLK
= 1.7 MHz if
1.2 V ≤ V
DD
< 1.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SYSTEM PERFORMANCE
Resolution 10 Bits
No missing codes 10 Bits
Integral linearity –0.5 0.5 LSB
(1)
Differential linearity –0.5 0.5 LSB
1.2 V ≤ V
DD
< 1.6 V –0.75 0.75
Offset error
(2)
LSB
1.6 V ≤ V
DD
≤ 3.6 V –1 1
1.2 V ≤ V
DD
< 1.6 V –0.5 0.5
Gain error
(3)
LSB
1.6 V ≤ V
DD
≤ 3.6 V –0.5 0.5
1.2 V ≤ V
DD
< 1.6 V –2 2
Total unadjusted error
(4)
LSB
1.6 V ≤ V
DD
≤ 3.6 V –2 2
SAMPLING DYNAMICS (See Timing Characteristics Section)
t
CONVERT
Conversion time f
SCLK
= 3.4 MHz, 11 SCLK cycles 3.235 µs
t
SAMPLE
Acquisition time f
SCLK
= 3.4 MHz, 1.6 V ≤ V
DD
≤ 3.6 V 0.64 µs
f
SAMPLE
Throughput rate f
SCLK
= 3.4 MHz, 1.6 V ≤ V
DD
≤ 3.6 V 240 KSPS
Aperture delay 10 ns
Aperture jitter 40 ps
DYNAMIC CHARACTERISTICS
f
SAMPLE
= 100 KSPS, f
IN
= 30 kHz, 1.2 V ≤ V
DD
< 1.6 V 61
Signal-to-noise
SINAD dB
and distortion
f
SAMPLE
= 200 KSPS, f
IN
= 30 kHz, 1.6 V ≤ V
DD
≤ 3.6 V 61 61.7
f
SAMPLE
= 100 KSPS, f
IN
= 30 kHz, 1.2 V ≤ V
DD
< 1.6 V 61.5
SNR Signal-to-noise ratio dB
f
SAMPLE
= 200 KSPS, f
IN
= 30 kHz, 1.6 V ≤ V
DD
≤ 3.6 V 61.8
f
SAMPLE
= 100 KSPS, f
IN
= 30 kHz, 1.2 V ≤ V
DD
< 1.6 V -68
THD Total harmonic distortion
(5)
dB
f
SAMPLE
= 200 KSPS, f
IN
= 30 kHz, 1.6 V ≤ V
DD
≤ 3.6 V -78 -72
f
SAMPLE
= 100 KSPS, f
IN
= 30 kHz, 1.2 V ≤ V
DD
< 1.6 V 73
SFDR Spurious free dynamic range dB
f
SAMPLE
= 200 KSPS, f
IN
= 30 kHz, 1.6 V ≤ V
DD
≤ 3.6 V 74 80
At 0.1 dB, 1.2 V ≤ V
DD
< 1.6 V 2
At 0.1 dB, 1.6 V ≤ V
DD
≤ 3.6 V 4
Full-power bandwidth
(6)
MHz
At 3 dB, 1.2 V ≤ V
DD
< 1.6 V 3
At 3 dB, 1.6 V ≤ V
DD
≤ 3.6 V 8
ANALOG INPUT
Full-scale input span
(7)
VIN – GND 0 V
DD
V
C
S
Input capacitance 12 pF
Input leakage current –1 1 µA
DIGITAL INPUT
Logic family, CMOS
1.2 V ≤ V
DD
< 1.6 V 0.7 × V
DD
3.6
1.6 V ≤ V
DD
< 1.8 V 0.7 × V
DD
3.6
V
IH
Input logic high level V
1.8 V ≤ V
DD
< 2.5 V 0.7 × V
DD
3.6
2.5 V ≤ V
DD
≤ 3.6 V 2 3.6
(1) LSB = Least Significant BIt
(2) The difference in the first code transition 000...000 to 000...001 from the ideal value of GND + 1 LSB.
(3) The difference in the last code transition 011...111 to 111...111 from the ideal value of V
DD
- 1 LSB with the offset error removed.
(4) The absolute difference from the ideal transfer function of the converter. This specification is similar to INL error except the effects of
offset error and gain error are included.
(5) The 2nd through 10th harmonics are used to determine THD.
(6) Input frequency where the amplitude of the digitized signal has decreased by 0.1 dB or 3 dB.
(7) Ideal input span which does not include gain or offset errors.
5