Datasheet

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PIN CONFIGURATION
3
2
4
6
(TOP VIEW)
1
REF/V
DD
GND
VIN
SCLK
ADS7866/67/68
DBV PACKAGE
CS
5
SDO
ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME NO.
REF/V
DD
1 External reference input and power supply
GND 2 Ground for signal and power supply. All analog and digital signals are referred with respect to this pin.
VIN 3 Analog signal input
SCLK 4 Serial clock input. This clock is used for clocking data out, and it is the source of conversion clock.
This is the serial data output of the conversion result. The serial stream comes with MSB first. The MSB is clocked out
(changed) on the falling edge one SCLK after the sampling period ends. This results in four leading zeros after CS
SDO 5
becomes active. SDO is 3-stated once all the valid bits are clocked out (12 for ADS7866, 10 for ADS7867, and 8 for
ADS7868).
This is an active low input signal. It is used as a chip select to gate the SCLK input, to initiate a conversion, and to
CS 6
frame output data.
10