Datasheet
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TIMING REQUIREMENTS
(1) (2)
1
2
3
5
4
6
10
16
14
12
1
9
SCLK
SDO
Hi−Z
Auto Power
−
Down
7
8
Last SCLK= 16 for ADS7866
14for ADS 7867
12for ADS 7868
Hi−Z
Auto Power
−
Down
2
t
SU(CSF−FSCLKF)
t
C(SCLK)
t
WH(SCLK)
t
WL(SCLK)
t
WH(CS)
t
SU(LSBZ−CSF)
t
DIS(EOC−SDOZ)
t
SU(CSF−FSCLKF)
t
D(CSF−SDOVALID)
“0” “0” “0”
t
CONVERT
“0” “0” “0”
t
H(SCLKF−SDOVALID)
t
D(SCLKF−SDOVALID)
t
D(CSF−SDOVALID)
t
SAMPLE
“0”
HOLD EOC
CS
t
CYCLE
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5
LSB
ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
At –40°C to 85°C, f
SCLK
= 3.4 MHz if 1.6 V ≤ V
DD
≤ 3.6 V; f
SCLK
= 1.7 MHz if 1.2 V ≤ V
DD
< 1.6 V, 50-pF Load on SDO Pin,
unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
sample
Sample time t
SU(CSF-FSCLKF)
+ 2 × t
C(SCLK)
µs
ADS7866 13 × t
C(SCLK)
t
convert
Conversion time ADS7867 11 × t
C(SCLK)
µs
ADS7868 9 × t
C(SCLK)
1.2 V ≤ V
DD
< 1.6 V See
(3)
100
1.6 V ≤ V
DD
< 1.8 V See
(3)
100
t
C(SCLK)
Cycle time µs
1.8 V ≤ V
DD
< 2.5 V See
(3)
50
2.5 V ≤ V
DD
≤ 3.6 V See
(3)
6.7
t
WH(SCLK)
Pulse duration 0.4 × t
C(SCLK)
0.6 × t
C(SCLK)
ns
t
WL(SCLK)
Pulse duration 0.4 × t
C(SCLK)
0.6 × t
C(SCLK)
ns
1.2 V ≤ V
DD
< 1.6 V 192
t
SU(CSF-FSCLKF)
Setup time 1.6 V ≤ V
DD
< 1.8 V 55 ns
1.8 V ≤ V
DD
≤ 3.6 V 55
1.2 V ≤ V
DD
< 1.6 V 65
t
D(CSF-SDOVALID)
Delay time 1.6 V ≤ V
DD
< 1.8 V 55 ns
1.8 V ≤ V
DD
≤ 3.6 V 55
1.2 V ≤ V
DD
< 1.6 V 20
t
H(SCLKF-SDOVALID)
Hold time 1.6 V ≤ V
DD
< 1.8 V 10 ns
1.8 V ≤ V
DD
≤ 3.6 V 10
1.2 V ≤ V
DD
< 1.6 V 140
t
D(SCLKF-SDOVALID)
Delay time 1.6 V ≤ V
DD
< 1.8 V 140 ns
1.8 V ≤ V
DD
≤ 3.6 V 140
1.2 V ≤ V
DD
< 1.6 V 10 80
t
DIS(EOC-SDOZ)
Disable time 1.6 V ≤ V
DD
< 1.8 V 7 60 ns
1.8 V ≤ V
DD
≤ 3.6 V 7 60
1.2 V ≤ V
DD
< 1.6 V 20
t
WH(CS)
Pulse duration 1.6 V ≤ V
DD
< 1.8 V 10 ns
1.8 V ≤ V
DD
≤ 3.6 V 10
1.2 V ≤ V
DD
< 1.6 V 20
t
SU(LSBZ-CSF)
Setup time 1.6 V ≤ V
DD
< 1.8 V 10 ns
1.8 V ≤ V
DD
≤ 3.6 V 10
(1) All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) See timing diagram in Figure 1 .
(3) Min t
C(SCLK)
is determined by the Min t
SAMPLE
of the specific resolution and supply voltage. See Acquisition Time, Conversion Time, and
Total Cycle Time section for further details.
Figure 1. Timing Diagram
9