Datasheet
www.ti.com
TYPICAL CONNECTION
REF/V
DD
GND
GND
0.1 F
REF3112
1.8 V
CS
SCLK
SDO
SS
SCK
MISO
VIN
Host
Processor
ADS7866/67/68
Analog Input
1.2 V
ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
THEORY OF OPERATION (continued)
Table 1. Acquisition, Conversion, SCLK, and Potential Throughput Calculation
PARAMETER SUPPLY VOLTAGE ADS7866 ADS7867 ADS7868 UNIT
1.2 V ≤ V
DD
< 1.6 V 192 192 192
MIN t
SU(CSF-FSCLKF)
Setup time 1.6 V ≤ V
DD
< 1.8 V 55 55 55 ns
1.8 V ≤ V
DD
≤ 3.6 V 55 55 55
1.2 V ≤ V
DD
< 1.6V 80 80 80
MAX t
DIS(EOC-SDOZ)
Disable time 1.6 V ≤ V
DD
< 1.8 V 60 60 60 ns
1.8 V ≤ V
DD
≤ 3.6 V 60 60 60
1.2 V ≤ V
DD
< 1.6 V 20 20 20
MIN t
SU(LSBZ-CSF)
Setup time 1.6 V ≤ V
DD
< 1.8 V 10 10 10 ns
1.8 V ≤ V
DD
≤ 3.6 V 10 10 10
1.2 V ≤ V
DD
< 1.6 V 1.7 1.7 1.7
MAX f
SCLK
Frequency 1.6 V ≤ V
DD
< 1.8 V 3.4 3.4 3.4 MHz
1.8 V ≤ V
DD
≤ 3.6 V 3.4 3.4 3.4
1.2 V ≤ V
DD
< 1.6 V 1368 1368 1368
MIN t
sample
Sample time 1.6 V ≤ V
DD
< 1.8 V 643 643 643 ns
1.8 V ≤ V
DD
≤ 3.6 V 643 643 643
1.2 V ≤ V
DD
< 1.6 V 7647 6471 5294
MIN t
convert
Conversion time 1.6 V ≤ V
DD
< 1.8 V 3824 3235 2647 ns
1.8 V ≤ V
DD
≤ 3.6 V 3824 3235 2647
1.2 V ≤ V
DD
< 1.6 V 9116 7939 6763
MIN t
CYCLE
Cycle time 1.6 V ≤ V
DD
< 1.8 V 4537 3949 3360 ns
1.8 V ≤ V
DD
≤ 3.6 V 4537 3949 3360
1.2 V ≤ V
DD
< 1.6 V 110 126 148
Theoretical sample fre-
f
sample
1.6 V ≤ V
DD
< 1.8 V 220 253 298 KSPS
quency
1.8 V ≤ V
DD
≤ 3.6 V 220 253 298
For a typical connection circuit for the ADS7866/67/68 see Figure 27 . A REF3112 is used to supply 1.2 V to the
device. A 0.1-µF decoupling capacitor is required between the REF/V
DD
and GND pins of the converter. This
capacitor should be placed as close as possible to the pins of the device. Designers should strive to minimize the
routing length of the traces that connect the terminals of the capacitor to the pins of the converter.
Keep in mind the converter offers no inherent rejection of noise or voltage variation in regards to the reference
input. This is of particular concern because the reference input is tied to the power supply. Any noise and ripple
from the supply appears directly in the digital results. While high frequency noise can be filtered out as described
in the previous paragraph, voltage variation due to the line frequency (50 Hz or 60 Hz) can be difficult to remove.
Figure 27. Typical Circuit Configuration
18