Datasheet

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4 Digital Interface
Digital Interface
Table 2. Jumper Setting
(1)
Jumper Setting
Reference
Description
Designator
1-2 2-3
Set negative supply of U2 to ground. Installed
(2)
SJP1
Select negative supply of U2 to -VCC. Not Installed
Set negative supply of U4 to ground. Not Installed
SJP2
Select negative supply of U4 to -VCC. Installed
(2)
Apply CS from P2.1 to the ADC Chip select pin Installed
(2)
W1
Apply FS from P2.7 to the ADC Chip select pin Not Installed
Set IOVDD to +3.3VD Installed
(2)
W2
Set IOVDD to +5VD N/A - Pin 3 Cut
Set 2.5 V to W4 (pin 3) Installed
(2)
W3
Set user applied voltage to W4 (pin 3) Not Installed
Set DUT power supply pin to 5 V N/A - Pin 1 Cut
W4
Set DUT power supply pin to voltage on W3 (pin 2). Installed
(2)
(1)
These jumper setting are for PWB revision B of the ADS7866EVM/7887EVM/7888EVM.
(2)
Factory Installed
The ADS7866EVM/ADS7867EVM/ADS7868EVM is designed for easy interfacing to multiple platforms.
Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient dual row
header/socket combination at P1 and P2. Consult Samtec at www.samtec.com or 1-800-SAMTEC-9 for a
variety of mating connector options.
The digital input and output signals for the converter is made available via connector P2 on the
ADS7866EVM/ADS7867EVM/ADS7868EVM, see Table 3 for connector pin-out.
Table 3. Serial Control Connector P2
Description Signal Name Connector.Pin Number Signal Name Description
Chip Select CS P2.1 P2.2 N/C Reserved
Serial Clock SCLK P2.3 P2.4 DGND Ground
Reserved N/C P2.5 P2.6 N/C Reserved
Frame Sync FS P2.7 P2.8 N/C Reserved
Reserved N/A P2.9 P2.10 DGND Ground
Reserved N/C P2.11 P2.12 N/C Reserved
Serial Data Out SDO P2.13 P2.14 N/C Reserved
Reserved N/C P2.15 P2.16 N/C Reserved
Reserved N/C P2.17 P2.18 DGND Ground
Reserved N/C P2.19 P2.20 N/A Reserved
I/O buffer and level translation functions may not be required for some applications. These devices have
the high-level digital input that is not limited to the device VDD voltage, but to 4 V. This means the ADC
can be powered up at 1.2 V and interfaced to 3.3-V logic directly.
The ADS7866/ADS7867/ADS7868 output low-level and high-level voltages are 0.4 V and VDD - 0.2 V,
respectively. If the ADS7866/ADS7867/ADS7868 is powered up at 3.6 V and the host processor is at
1.8 V, then level translation maybe required. The output level translation function (done by U6 on the
EVM) may be required depending on the host processor. Check your host processor’s data sheet for input
logic levels.
ADS7866EVM/ADS7867EVM/ADS7868EVM 4 SLAU181 – July 2006
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