ADS7864 SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 500kHz, 12-Bit, 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION • • • • • • • • The ADS7864 is a dual 12-bit, 500kHz analog-to-digital (A/D) converter with 6 fully differential input channels grouped into three pairs for high speed simultaneous signal acquisition.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 44 43 42 41 40 39 CH A0− CH B0+ CH B0− CH C0+ CH C0− CH C1− CH C1+ CH B1− CH B1+ 38 37 CH A1− 45 CH A1+ 46 +VA 36 AGND AGND 35 3 DB15 REFIN 34 4 DB14 REFOUT 33 5 DB13 RESET 32 6 DB12 A0 31 7 DB11 A1 30 8 DB10 A2 29 1 +VA 2 0.1µF 0.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 ELECTRICAL CHARACTERISTICS All specifications TMIN to TMAX, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz (unless otherwise noted). PARAMETER TEST CONDITIONS ADS7864Y MIN TYP Resolution ADS7864YB MAX MIN TYP 12 MAX 12 UNIT Bits Analog Input Input Voltage Range-Bipolar Absolute Input Range VCENTER = +2.5V –VREF +VREF +IN –0.3 +VA + 0.3 –IN –0.3 +VA + 0.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications TMIN to TMAX, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz (unless otherwise noted). PARAMETER ADS7864Y TEST CONDITIONS MIN ADS7864YB TYP MAX MIN TYP MAX UNIT Digital Input/Output Logic Family CMOS CMOS Logic Levels: VIH IIH = +5µA 3.0 +VD + 0.3 3.0 +VD + 0.3 V VIL IIL = +5µA –0.3 0.8 –0.3 0.8 V VOH IOH = –500µA 3.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 PIN DESCRIPTIONS 6 PIN NAME 1 +VA DESCRIPTION 2 AGND Analog Ground 3 DB15 Data Valid Output: ‘1’ for data valid; ‘0’ for invalid data.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 TYPICAL CHARACTERISTICS All specifications TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz (unless otherwise noted) FREQUENCY SPECTRUM (4096 Point FFT; fIN = 199.9kHz, -0.2dB) 0 0 −20 −20 −40 −40 Amplitude (dB) Amplitude (dB) FREQUENCY SPECTRUM (4096 Point FFT; fIN = 99.9kHz, –0.2dB) −60 −80 −100 −60 −80 −100 −120 −120 0 62.5 125 187.5 250 0 62.5 125 Frequency (kHz) Figure 1.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 TYPICAL CHARACTERISTICS (continued) All specifications TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz (unless otherwise noted) POSITIVE GAIN MATCH vs TEMPERATURE (Maximum Deviation for All Six Channels) 1.0 1.80 Change in Positive Gain Match (LSB) THD and SFDR Delta from +25 C (dB) CHANGE IN SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs TEMPERATURE THD 0.5 0.0 SFDR −0.5 −1.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 TYPICAL CHARACTERISTICS (continued) All specifications TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz (unless otherwise noted) DIFFERENTIAL LINEARITY ERROR vs CODE INTEGRAL LINEARITY ERROR vs CODE 2.0 1 Typical of All Six Channels 1.5 0.5 1.0 0.25 0.5 ILE (LSB) DLE (LSB) Typical of All Six Channels 0.75 0 −0.25 −0.5 −0.5 −1.0 −0.75 −1.5 −1 800 000 −2.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 TYPICAL CHARACTERISTICS (continued) All specifications TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz (unless otherwise noted) INTEGRAL LINEARITY ERROR MATCH vs CODE Channel A0/Channel B0 (Same Converter, Different Channels) DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 1.0 0.8 0.8 0.6 Positive DLE 0.6 0.4 0.2 ILE (LSB) DLE (LSB) 0.4 0 −0.2 −0.4 0 −0.2 −0.4 Negative DLE −0.6 −0.6 −0.8 −40 0.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 APPLICATIONS INFORMATION INTRODUCTION The ADS7864 is a high speed, low power, dual 12-bit analog-to-digital converter (ADC) that operates from a single +5V supply. The input channels are fully differential with a typical common-mode rejection of 80dB. The part contains dual 2µs successive approximation ADCs, six differential sample-and-hold amplifiers, an internal +2.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 +IN CM +VREF +VREF CM Voltage −IN = CM Voltage −VREF CM −VREF CM +1/2VREF t Single−Ended Inputs +IN +VREF CM Voltage CM −1/2VREF −VREF −IN t Differential Inputs NOTES: Common−Mode Voltage (Differential Mode) = (IN+) − (IN−) , Common−Mode Voltage (Single−Ended Mode) = IN−. 2 The maximum differential voltage between +IN and −IN of the ADS7864 is VREF.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 In each case, care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. Otherwise, this may result in offset error, which will change with both temperature and input voltage. The input current on the analog inputs depend on a number of factors: sample rate, input voltage, and source impedance.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 BIPOLAR INPUTS The differential inputs of the ADS7864 were designed to accept bipolar inputs (–VREF and +VREF) around the internal reference voltage (2.5V), which corresponds to a 0V to 5V input range with a 2.5V reference. By using a simple op amp circuit featuring a single amplifier and four external resistors, the ADS7864 can be configured to accept bipolar inputs. The conventional ±2.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 other channels are already in the hold mode but not converted, then the conversion of channel X is put in the queue until the previous conversion has been completed. If more than one channel goes into hold mode within one clock cycle, then channel A will be converted first if HOLDA is one of the triggered hold signals. Next, channel B will be converted, and last, channel C.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 t11 BUSY t4 t10 CLOCK HOLDB CS RD A0 Figure 27. Timing of One Conversion Cycle READING DATA (RD, CS)—In general, the channel/data outputs are in tristate. Both CS and RD have to be low to enable these outputs. RD and CS have to stay low together for at least 30ns (see Figure 28, t13) before the output data is valid. RD has to remain high for at least 30ns (see Figure 28, t14) before bringing it back low for a subsequent read command.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 Table 2. Channel Truth Table OUTPUT CODE (DB15…DB0) The ADS7864 has a 16-bit output word. DB15 is ‘1’ if the output contains valid data. This is important for the FIFO mode. Valid Data can be read until DB15 switches to 0. DB14, DB13 and DB12 store channel information as indicated in Table 2 (Channel Truth Table). The 12-bit output data is stored from DB11 (MSB) to DB0 (LSB).
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 GETTING DATA The ADS7864 has three different output modes that are selected with A2, A1 and A0. A2A1A0 are only active when RD and CS are both low. After a reset occurs, A2A1A0 are set to 000. With (A2 A1 A0) = 000 to 101 a particular channel can directly be addressed (see Table 3 and Figure 27). The channel address should be set at least 10ns (see Figure 28, t12) before the falling edge of RD and should not change as long as RD is low.
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 At time tB a HOLDB signal occurs. With the next falling clock edge (tC) the ADS7864 puts channel B into the loop to be converted next. As the reset signal occurred at tA, the conversion of channel B will be started with the next rising edge of the clock after tC. Bit 15 shows if the FIFO is empty (low) or if it contains channel information (high). Bits 12 to 14 contain the Channel for the 12-bit data word (Bit 0 to 11).
ADS7864 www.ti.com SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS7864 circuitry. This is particularly true if the CLOCK input is approaching the maximum throughput rate. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com (4) 24-Jan-2013 Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7864Y/250 TQFP PFB 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 ADS7864Y/2K TQFP PFB 48 2000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 ADS7864YB/250 TQFP PFB 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7864Y/250 TQFP PFB ADS7864Y/2K TQFP PFB 48 250 367.0 367.0 38.0 48 2000 367.0 367.0 38.0 ADS7864YB/250 TQFP PFB ADS7864YB/2K TQFP PFB 48 250 367.0 367.0 38.0 48 2000 367.0 367.0 38.
MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
