Datasheet

www.ti.com
4.2 Parallel Data
4.3 GPIO/Control Options
5 Power Supplies
Power Supplies
Table 2. Header/Socket Combination at J5
Pin Number Signal Description
J5.1 DC_CSa Daughter Card Chip Select – active-low signal used to access the EVM
J5.3 DC_AWE Write Strobe – signal not used on the ADS7864MEVM
J5.5 DC_ARE Read Strobe – active low signal used to access parallel data
J5.7 EVM_A0 EVM Address line 0 – used with U3 to control A0
J5.9 EVM_A1 EVM Address line 1 – used with U3 to control A1
J5.11 EVM_A2 EVM Address line 2 – used with U3 to control A2
J5.13 EVM_A3 EVM Address line 3 – used with U3 and U6 to control /CS
J5.15 EVM_A4 EVM Address line 4 – not used
J5.17 DC_TOUT Timer Input – optional CLK input used with W8
J5.19 DC_INTa Interrupt Output to Host Processor – connects to the ADC's EOC pin
The ADS7864MEVM uses Samtec part numbers SSW-116-22-F-D-VS-K and TSM-116-01-T-DV-P provide
a convenient 16-pin, dual-row, header/socket combination at J6. This header/socket combination provides
access to the parallel data pins of the ADS7864. Data line D0 is connected to J6 pin 1. Data lines 1–15
are located on pins 3–31, respectively. Even pin numbers 2–32 are connected to digital ground
Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P also provide a 10-pin, dual-row
header/socket combination at J1 to facilitate general-purpose input/output (GPIO) control options to the
ADS7864. Table 3 describes the functions and pinout of J1.
Table 3. J1 Pinout and Functions
Pin Number Signal Description
J1.1 NA Unused on the ADS7864MEVM
J1.3 NA Unused on the ADS7864MEVM
J1.5 HOLD_C# Active low signal HOLDC used to start a conversion on ADC channel pair C
J1.7 HOLD_B# Active low signal HOLDB used to start a conversion on ADC channel pair B
J1.9 HOLD_A# Active low signal HOLDA used to start a conversion on ADC channel pair A
J1.11 RESET# Active low signal RESET used to place the ADS7864’s FIFO in reset state
J1.13 NA Unused on the ADS7864MEVM
J1.15 NA Unused on the ADS7864MEVM
J1.17 DC_TOUTa Used in conjunction with W10 to allow host processor timer control of HOLDx
J1.19 NA Unused on the ADS7864MEVM
The ADS7864MEVM board requires +5 VDC for the both the analog and digital section of the ADC. The
supply (+Va and +Vd) can range from +4.75 VDC to +5.25 VDC. Because the EVM is designed to work
with the 5-6K and HPA-MCU Interface Boards, JP1 provides direct connection to the common power bus
described in SLAU104 . Table 4 shows the pinout of JP1:
SLAU188 – September 2006 ADS7864MEVM 5
Submit Documentation Feedback