Datasheet

CLOCK
CONVST
10ns
Cyc el 1
Cyc el 2
A
B C
10ns
5ns 5ns
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SBAS383E –JUNE 2007–REVISED JANUARY 2011 www.ti.com
TIMING CHARACTERISTICS (continued)
NOTE: All CONVST commands that occur more than 10ns before the rising edge of cycle ‘1’ of the external clock
(Region ‘A’) initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands that occur 5ns after the rising
edge of cycle ‘1’ or 10ns before the rising edge of cycle 2 (Region ‘B’) initiate a conversion on the rising edge of cycle
‘2’. All CONVST commands that occur 5ns after the rising edge of cycle ‘2’ (Region ‘C’) initiate a conversion on the
rising edge of the next clock period.
The CONVST pin should never be switched from LOW to HIGH in the region 10ns prior to the rising edge of the
CLOCK and 5ns after the rising edge (gray areas). If CONVST is toggled in this gray area, the conversion could begin
on either the same rising edge of the CLOCK or the following edge.
Figure 2. CONVST Timing
TIMING REQUIREMENTS
(1)
Over recommended operating free-air temperature range at –40°C to +125°C, AV
DD
= 5V, and BV
DD
= 2.7V to 5V, unless
otherwise noted.
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SYMBOL PARAMETER COMMENTS MIN MAX UNIT
t
CONV
Conversion time f
CLOCK
= 32MHz 406.25 ns
t
ACQ
Acquisition time f
CLOCK
= 32MHz 62.5 ns
f
CLOCK
CLOCK frequency See Figure 1 1 32 MHz
t
CLOCK
CLOCK period See Figure 1 31.25 1000 ns
t
CKL
CLOCK low time See Figure 1 9.4 ns
t
CKH
CLOCK high time See Figure 1 9.4 ns
t
1
CONVST high time See Figure 1 20 ns
t
2
SDI setup time to CLOCK falling edge See Figure 1 10 ns
t
3
SDI hold time to CLOCK falling edge See Figure 1 5 ns
t
4
RD high setup time to CLOCK falling edge See Figure 1 10 ns
t
5
RD high hold time to CLOCK falling edge See Figure 1 5 ns
t
6
CONVST low time See Figure 1 1 t
CLOCK
t
7
RD low time relative to CLOCK falling edge See Figure 1 1 t
CLOCK
t
8
CS low to SDOx valid See Figure 1 13 ns
See Figure 1,
4 11 ns
CLOCK rising edge to DATA valid delay
2.7V ≤ BV
DD
≤ 3.6V
t
9
(MIN = minimum hold time of current data;
See Figure 1,
MAX = maximum delay to new data valid)
3 9 ns
4.5V ≤ BV
DD
≤ 5.5V
t
10
CONVST rising edge to BUSY high delay
(2)
See Figure 1 3 ns
t
11
CLOCK rising edge to BUSY low delay See Figure 1 3 ns
t
12
CS low to RD high delay See Figure 1 10 ns
(1) All input signals are specified with t
R
= t
F
= 1.5ns (10% to 90% of BV
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) Not applicable in auto-NAP power-down mode.
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