Datasheet

ADS7863
www.ti.com SBAS383E –JUNE 2007–REVISED JANUARY 2011
LAYOUT Depending on the circuit density of the board,
placement of the analog and digital components, and
For optimum performance, care should be taken with
the related current loops, a single solid ground plane
the physical layout of the ADS7863 circuitry. This
for the entire printed circuit board (PCB) or a
condition is particularly true if the CLOCK input is
dedicated analog ground area may be used. In an
approaching the maximum throughput rate. In this
instance of a separated analog ground area, ensure a
case, it is recommended to have a fixed phase
low-impedance connection between the analog and
relationship between CLOCK and CONVST. The best
digital ground of the ADC by placing a bridge
performance can be achieved when the digital
underneath (or next to) the ADC. Otherwise, even
interface is run in SPI mode; thus, the CLOCK signal
short undershoots on the digital interface with a value
is switched off after the 16th cycle and remains low
lower than –300mV lead to conduction of ESD
when CONVST is issued.
diodes, causing current flow through the substrate
and degrading the analog performance.
Additionally, the basic SAR architecture is quite
sensitive to glitches or sudden changes on the power
During the PCB layout, care should also be taken to
supply, reference, ground connections, and digital
avoid any return currents crossing any sensitive
inputs that occur just before latching the output of the
analog areas or signals. No signal must exceed the
analog comparator. Therefore, when driving any
limit of –300mV with respect to the according ground
single conversion for an n-bit SAR converter, there
plane. Figure 42 illustrates the recommended layout
are n windows in which large external transient
of the ground and power-supply connections for both
voltages can affect the conversion result. Such
package options.
glitches might originate from switching power
supplies, nearby digital logic, or high-power devices.
Supply
The degree of error in the digital output depends on
the reference voltage, layout, and the exact timing of The ADS7863 has two separate supplies: the BV
DD
the external event. These errors can change if the pin for the digital interface and the AV
DD
pin for all
external event also changes in time with respect to remaining circuits.
the CLOCK input.
BV
DD
can range from 2.7V to 5.5V, allowing the
With this possibility in mind, power to the ADS7863 ADS7863 to easily interface with processors and
should be clean and well-bypassed. A 0.1mF ceramic controllers. To limit the injection of noise energy from
bypass capacitor should be placed as close to the external digital circuitry, BV
DD
should be filtered
device as possible. In addition, a 1mF to 10mF properly. Bypass capacitors of 0.1mF and 10mF
capacitor is recommended. If needed, an even larger should be placed between the BV
DD
pin and the
capacitor and a 5Ω or 10Ω series resistor may be ground plane.
used to low-pass filter a noisy supply.
AV
DD
supplies the internal analog circuitry. For
If the reference voltage is external and originates optimum performance, a linear regulator (for
from an operational amplifier, be sure that it can drive example, the UA7805 family) is recommended to
the reference capacitor without oscillation. The generate the analog supply voltage in the range of
connection between the output of the external 2.7V to 5.5V for the ADS7863 and the necessary
reference driver and REF
IN
should be of low analog front-end circuitry.
resistance (10Ω max) to minimize any
Bypass capacitors should be connected to the ground
code-dependent voltage drop on this path.
plane such that the current is allowed to flow through
the pad of the capacitor (that is, the vias should be
Grounding
placed on the opposite side of the connection
The xGND pins should be connected to a clean between the capacitor and the power-supply pin of
ground reference. These connections should be kept the ADC).
as short as possible to minimize the inductance of
these paths. It is recommended to use vias Digital Interface
connecting the pads directly to the ground plane. In
To further optimize device performance, a resistor of
designs without ground planes, the ground trace
10Ω to 100Ω can be used on each digital pin of the
should be kept as wide as possible. Avoid
ADS7863. In this way, the slew rate of the input and
connections that are too near the grounding point of a
output signals is reduced, limiting the noise injection
microcontroller or digital signal processor.
from the digital interface.
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