Datasheet

f =
-3dB
ln(2) 2´
2 16 Tp ´ ´
CLK
ADS7863
www.ti.com SBAS383E –JUNE 2007–REVISED JANUARY 2011
REF
IN
ADS7861 COMPATIBILITY
The ADS7863 offers an unbuffered REF
IN
input with a
The ADS7863IDBQ is pin-compatible with the
code-dependent input impedance while featuring a
ADS7861E/EB/EG4. However, there are some
programmable and buffered reference output
differences between the two devices that must be
(REF
OUT
). The ADS7861 offers a high-impedance
considered when migrating from the ADS7861 to the
(buffered) reference input. If an existing
ADS7863 in an existing design.
ADS7861-based design uses the internal reference of
the device and relies on an external resistor divider to
SDI versus A0
adjust the input voltage range of the ADC, migration
One of the differences is that pin 16 (A0), which
to ADS7863 requires one of the following conditions:
updates the internal SDI register of the ADS7863, is
• a software change to setup the internal reference
used in conjunction with M0 to select the input
DAC properly via SDI while removing the external
channel on the ADS7861.
resistors; or
If, in an existing design, the ADS7861 is used in
• an additional external buffer between the resistor
two-channel mode (M0 = '0') and the status of the A0
divider and the required 470nF (minimum)
pin is unchanged within the first four clock cycles
capacitor on the REF
IN
input.
after issuing a conversion start (rising edge of
In the latter case, while the capacitor stabilizes the
CONVST), the ADS7863 would act similarly to the
reference voltage during the entire conversion, the
ADS7861 and convert either channels CHx0 (if SDI is
buffer has to re-charge it by providing an average
held low during the entire period) or channels CHx1
current only; thus the required minimum bandwidth of
(if SDI is held high during the entire period).
the buffer can be calculated using Equation 2:
Figure 33 describes the behavior of the ADS7863 in
such a situation.
(2)
The ADS7863 can also be used to replace the
ADS7861 when run in four-channel mode (M0 = '1').
The buffer must also be capable of driving the 470nF
In this case, the A0 pin is held static (high or low)
load while maintaining its stability.
which is also required in the case of SDI to prevent
accidental update of the SDI register.
Timing
In both cases described above, the additional
The only timing requirement that may cause the
features of the ADS7863 (pseudo-differential input
ADS7863 to malfunction in an existing
mode, programmable reference voltage output, and
ADS7861-based design is the CONVST high time (t
1
)
the different power-down modes) could not be
which is specified to be 20ns minimum while the
accessed but the hardware and software would
ADS7861 works properly with a pulse as short as
remain backward-compatible to the ADS7861.
15ns. All the other required minimum setup and hold
times are specified to be either the same as or lower
than the ADS7863; therefore, there are no conflicts
with the ADS7861 requirements.
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