Datasheet

ADS7863
SBAS383E –JUNE 2007–REVISED JANUARY 2011 www.ti.com
Power-Down Modes and Reset
The auto-nap power-down mode is very similar to
(Not ADS7861-Compatible)
the nap mode. The only differences are the methods
of powering down and waking up the device. The SDI
The ADS7863 has a comprehensive built-in
Register bit AN is only used to enable/disable this
power-down feature. There are three power-down
feature. If the auto-nap mode is enabled, the
modes: deep power-down, nap power-down, and
ADS7863 turns off the biasing automatically after
auto-nap power-down. All three power-down modes
finishing a conversion; thus, the end of conversion
are activated with the 12th falling CLOCK edge of the
actually activates the auto-nap power-down. The
SDI access, during which the related bit asserts (DP
device powers down within 200ns in this mode, as
= '1', N = '1', or AN = '1'). All modes are deactivated
well. Triggering a new conversion by applying a
by de-asserting the respective bit in the SDI Register.
CONVST pulse puts the device back into normal
Contents of the SDI Register are not affected by any
operation and automatically starts a new conversion
of the power-down modes. Any ongoing conversion
six CLOCK cycles later. Therefore, a complete
aborts when deep or nap power-down is initiated.
conversion cycle takes 19 CLOCK cycles; thus, the
Table 10 lists the differences among the three
maximum throughput rate in auto-nap power-down
power-down modes.
mode is reduced to 1.68MSPS.
In deep power-down mode, all functional blocks
To issue a device reset, an RD pulse must be
except the digital interface are disabled. The analog
generated along with an SDI word containing A[2:0] =
block has its bias currents turned off. In this mode,
'101'. With the 12th falling edge after generating the
the power dissipation reduces to 1mA within 2ms. The
RD pulse, the entire device—including the serial
wake-up time from deep power-down mode is 1ms.
interface—is forced into reset. After approximately
In nap power-down mode, the ADS7863 turns off
500ns, the serial interface becomes active again.
the biasing of the comparator and the mid-voltage
buffer within 200ns. The device goes into nap
power-down mode regardless of the conversion state.
Table 10. Power-Down Modes
POWER-DOWN ENABLED ACTIVATION RESUMED DISABLED
TYPE BY ACTIVATED BY TIME BY REACTIVATION TIME BY
Deep DP = ‘1’ 13th clock 2ms DP = ‘0’ 1ms DP = ‘0’
Nap N = ‘1’ 13th clock 200ns N = ‘0’ 3 clocks N = ‘0’
Each end of
Auto-nap AN = ‘1’ 200ns CONVST pulse 3 clocks AN = ‘0’
conversion
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