Datasheet

C[1:0]isIgnored
P[1:0]='01' FeaturesON®
® S4='1'
C[1:0]isIgnored
P[1:0]='11' NoUpdates®
C[1:0]isIgnored
P[1:0]='11' NoUpdates®
C[1:0]isIgnored
P[1:0]='11' NoUpdates®
0B 1A0ACHX
CHX
1B 0A
12-Bit
DataCHB1
12-Bit
DataCHA0
12-Bit
DataCHA0
12-Bit
DataCHB0
12-Bit
DataCHA1
Previous12-Bit
DataCHAx
Previous12-Bit
DataCHBx
High-Z
NoConversion,
ReadAccessOnly
NoConversion,
ReadAccessOnly
Conversion
ofBothCHx0
Conversion
ofBothCHx1
Conversion
ofBothCHx0
PreviousConversion
ofBothCHxx
0 sm 0.5 sm 1.0 sm 1.5 sm 2.0 sm 2.5 sm 3.0 sm
1
16
1
16
1
16
1
16
1
16
1
1
CLOCK
CONVST
SDI
M0
M1
RD
CS
SDOA
SDOB
BUSY
Bothchannel0sareconvertedfirst,
followedbyconversionofbothchannel1s.
® S4Still='1' ® S4Still='1' ® S4Still='1'
ADS7863
SBAS383E –JUNE 2007–REVISED JANUARY 2011 www.ti.com
SPECIAL MODE IV (Not ADS7861-Compatible)
As with Special Mode II, these two pins do not need
to be issued every 16 CLOCK cycles. Data are
Analogous to Special Mode II, the ADS7863 also
available on the SDOA pin.
offers a special read mode for Mode IV in which both
data results of a conversion can be read, triggered by
This special read mode (shown in Figure 37) is not
a single RD pulse. In this case as well, bit S4 in the
available in Mode I or Mode III.
SDI register must be set to '1' while the CONVST and
RD pins can still be tied together .
Figure 37. Special Mode IV Timing Diagram (M0 = 1; M1 = 1; S4 = 1)
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Product Folder Link(s): ADS7863