Datasheet

Every2nd
CONVST
IsIgnored
Every2nd
CONVST
IsIgnored
Every2nd
CONVST
IsIgnored
C[1:0]='00' CHx0Next®
P[1:0]='00' NoFeatures®
C[1:0]IsIgnored
P[1:0]='00’ NoFeatures®
C[1:0]IsIgnored
P[1:0]='11’ NoFeatures®
C[1:0]IsIgnored
P[1:0]='00’ NoFeatures®
A A A
CHx
B B
CHx
12-Bit
DataCHB1
12-Bit
DataCHA0
12-Bit
DataCHA0
12-Bit
DataCHB0
12-Bit
DataCHA1
Previous12-Bit
DataCHAx
DataCHBx
High-Z
NoConversion,
ReadAccessOnly
NoConversion,
ReadAccessOnly
Conversion
ofBothCHx0
Conversion
ofBothCHx1
Conversion
ofBothCHx0
PreviousConversion
ofBothCHxx
0 sm 0.5 sm 1.0 sm 1.5 sm 2.0 sm 2.5 sm 3.0 sm
1
16
1
16
1
16
1
16
1
16
1 1
CLOCK
CONVST
SDI
M0
M1
RD
CS
SDOA
SDOB
BUSY
Previous12-Bit
DataCHBx
C[1:0]='11’ CHx1Next®
P[1:0]='11’ NoFeatures®
C[1:0]='00' CHx0Next®
P[1:0]='00’ NoFeatures®
ADS7863
SBAS383E –JUNE 2007–REVISED JANUARY 2011 www.ti.com
MODE II
from both ADCs (instead of 16 cycles, if M1 = '0'), the
ADS7863 requires 1.0ms to perform a complete
With M0 = '0' and M1 set to '1', the ADS7863 also
conversion/read cycle. If the CONVST signal is
operates in manual channel control mode and outputs
issued every 0.5ms (required for the RD signal) as in
data on the SDOA pin only while SDOB is set to
Mode I, every second pulse is ignored; see Figure 33.
3-state. All other pins function in the same manner as
they do in Mode I.
The output data consist of a '0' followed by an ADC
indicator ('0' for CHAx or '1' for CHBx), 12 bits of
Because it takes 32 clock cycles to output the results
conversion results, and another '00'.
Figure 33. Mode II Timing Diagram (M0 = 0; M1 = 1)
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Product Folder Link(s): ADS7863