Datasheet

C[1:0]='11' ConvertCHx1Next®
P[1:0]='11' SDIFeaturesNotUsed®
C[1:0]='00' ConvertCHx0Next®
P[1:0]='00' SDIFeaturesNotUsed®
C[1:0]='00' ConvertCHx0Next®
P[1:0]='00' SDIFeaturesNotUsed®
0 0
Previous12-BitDataCHAx
12-BitDataCHA1
High-Z
High-Z
12-BitDataCHB1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
PreviousConversionofBothCHxx ConversionofBothCHx1 ConversionofBothCHx0
1.0 sm0.5 sm0 sm
1 16 1 16
CLOCK
CONVST
SDI
M0
M1
RD
CS
SDOA
SDOB
BUSY
Previous12-BitDataCHBx
ADS7863
www.ti.com SBAS383E –JUNE 2007–REVISED JANUARY 2011
MODE I
After some delay (t
12
), the BUSY output pin goes high
and remains high for the duration of the conversion
With the M0 and M1 pins both set to '0', the ADS7863
cycle. On the falling edge of the second CLOCK
enters manual channel control operation and outputs
cycle, the ADS7863 latches in the channel for the
data on both SDOA and SDOB, respectively. The SDI
next conversion cycle, depending on the status of the
pin switches between the channels. A conversion is
SDI Register bits C[1:0]. CS must be brought low to
initiated by bringing CONVST high.
enable both serial outputs. Data are valid on the
16 clock cycles are required to perform a single falling edge of every 16 clock cycles per conversion.
conversion. With the rising edge of CONVST, the The first two bits are set to '0'. The subsequent data
ADS7863 switches asynchronously to the external contain the 12-bit conversion result (the most
CLOCK from sample to hold mode. significant bit is transferred first), followed by two '0's
(see Figure 1 and Figure 32).
Figure 32. Mode I Timing Diagram (M0 = 0; M1 = 0)
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