Datasheet

f =
-3dB
ln(2) (n+1)´
2 tp ´
ACQ
ADS7863
www.ti.com SBAS383E –JUNE 2007–REVISED JANUARY 2011
CONVST
The minimum –3dB bandwidth of the driving
operational amplifier can be calculated as shown in
The analog inputs are held with the rising edge of the
Equation 1, with n = 12 being the resolution of the
CONVST (conversion start) signal. The setup time of
ADS7863:
CONVST referred to the next rising edge of CLOCK
(system clock) is 10ns (minimum). The conversion
automatically starts with the rising CLOCK edge.
(1)
CONVST should not be issued during a conversion,
that is, when BUSY is high.
With t
ACQ
= 62.5ns, the minimum bandwidth of the
driving amplifier is 23MHz. The required bandwidth
RD (read data) and CONVST can be shorted to
can be lower if the application allows a longer
minimize necessary software and wiring. The RD
acquisition time.
signal is triggered by the ADS7863 on the falling
edge of CLOCK. Therefore, the combined signals
A gain error occurs if a given application does not
must be activated with the rising CLOCK edge. The
fulfill the settling requirement shown in Equation 1. As
conversion then starts with the subsequent rising
a result of precharging the capacitors, linearity and
CLOCK edge.
THD are not directly affected, however.
The OPA365 from Texas Instruments is
CLOCK
recommended as a driver; in addition to offering the
The ADC uses an external clock in the range of
required bandwidth, it provides a low offset and also
1MHz to 32MHz. 12 clock cycles are needed for a
offers excellent THD performance.
complete conversion; the following clock cycle is used
The phase margin of the driving operational amplifier
for pre-charging the sample capacitors and a
is usually reduced by the ADC sampling capacitor. A
minimum of two clock cycles are required for the
resistor placed between the capacitor and the
sampling. With a minimum of 16 clocks used for the
amplifier limits this effect; therefore, an internal 200Ω
entire process, one clock cycle is left for the required
resistor (R
SER
) is placed in series with the switch. The
setup and hold times along with some margin for
switch resistance (R
SW
) is typically 50Ω (see
delay caused by layout. The clock input can remain
Equivalent Input Circuit).
low between conversions (after applying the 16th
falling edge to complete a running conversion). It can
The differential input voltage range of the ADC is
also remain low after applying the 14th falling edge
±V
REF
, the voltage at the REF
IN
pin.
during a DAC register write access if the device is not
It is important to keep the voltage to all inputs within
required to perform a conversion on CHBx (for
the 0.3V limit below AGND and above AV
DD
while not
example, during an initiation phase after power-up).
allowing dc current to flow through the inputs. Current
The CLOCK duty cycle should be 50%. However, the
is only necessary to recharge the sample-and-hold
ADS7863 functions properly with a duty cycle
capacitors.
between 30% and 70%.
Analog-to-Digital Converter (ADC)
The ADS7863 includes two SAR-type, 2MSPS, 12-bit
ADCs (shown in the functional block diagram on the
front page of this data sheet).
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