Datasheet

Input
MUX
ADC+
ADC-
CHx1+
CHx1-
CHx0+
CHx0-
ADS7863
SBAS383E –JUNE 2007–REVISED JANUARY 2011 www.ti.com
APPLICATIONS INFORMATION
GENERAL DESCRIPTION
The ADS7863 includes two 12-bit analog-to-digital
converters (ADCs) that operate based on the
successive-approximation register (SAR) principle.
The ADCs sample and convert simultaneously.
Conversion time can be as low as 406.25ns. Adding
the acquisition time of 62.5ns and an additional clock
cycle for setup/hold time requirements and skew
Figure 31. Input Multiplexer Configuration
results in a maximum conversion rate of 2MSPS.
Each ADC has a fully differential, 2:1 multiplexer
The input path for the converter is fully differential
front-end. In many common applications, all negative
and provides a common-mode rejection of 72dB at
input signals remain at the same constant voltage (for
100kHz. The high CMRR also helps suppress noise
example, 2.5V). In this type of application, the
in harsh industrial environments.
multiplexer can be used in a pseudo-differential 3:1
mode, where CHx0– functions as a common-mode
Table 1. Fully Differential 2:1 Multiplexer
Configuration
input and the remaining three inputs (CHx0+, CHx1–,
and CHx1+) operate as separate inputs referred to
C1 C0 ADC+ ADC–
the common-mode input.
0 0 CHx0+ CHx0–
The ADS7863 also includes a 2.5V internal reference.
1 1 CHx1+ CHx1–
The reference drives a 10-bit digital-to-analog
converter (DAC), allowing the voltage at the REF
OUT
Table 2. Pseudo-Differential 3:1 Multiplexer
pin to be adjusted via the serial interface in 2.44mV
Configuration
steps. A low-noise operational amplifier with unity
C1 C0 ADC+ ADC–
gain buffers the DAC output voltage and drives the
REF
OUT
pin.
0 0 CHx0+ CHx0–
0 1 CHx1– CHx0–
The ADS7863 offers a serial interface that is
1 0 CHx1+ CHx0–
compatible with the ADS7861. However, instead of
the A0 pin of the ADS7861 that controls the channel
Each of the 2pF sample-and-hold capacitors (shown
selection, the ADS7863 offers a serial data input
as C
S
in the Equivalent Input Circuit) is connected via
(SDI) pin that supports additional functions described
switches to the multiplexer output. Opening the
in the Digital section of this data sheet (see also the
switches holds the sampled data during the
ADS7861 Compatibility section).
conversion process. After finishing the conversion,
both capacitors are pre-charged for the duration of
ANALOG
one clock cycle to the voltage present at the REF
IN
This section addresses the analog input circuit, the
pin. After the pre-charging, the multiplexer outputs
ADCs, and the reference design of the device.
are connected to the sampling capacitors again. The
voltage at the analog input pin is usually different
Analog Inputs
from the reference voltage; therefore, the sample
capacitors must be charged to within one-half LSB for
Each ADC is fed by an input multiplexer; see
12-bit accuracy during the acquisition time t
ACQ
(see
Figure 31. Each multiplexer is either used in a
the Timing Characteristics).
fully-differential 2:1 configuration (as described in
Table 1) or a pseudo-differential 3:1 configuration (as
Acquisition time is indicated with the BUSY signal
shown in Table 2). The channel selection is
being held low. It starts by closing the input switches
performed using bits C1 and C0 in the SDI register
(after finishing the previous conversion and
(see also the Serial Data Input section).
pre-charging) and finishes with the rising edge of the
CONVST signal. If the ADS7863 operates at full
speed, the acquisition time is typically 62.5ns.
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