Datasheet

ADS7852
SBAS111C
11
READING DATA
Data from the ADS7852 will appear at pins 15 through 26.
The MSB will output on pin 15 while the LSB will output
on pin 26. The outputs are coded in Straight Binary (with
0V = 000
H
and 5V = FFF
H
). Following a conversion, the
BUSY pin will go HIGH. After BUSY has been HIGH for
at least t
14
seconds, the CS and RD pins may be brought
LOW to enable the 12-bit output bus. CS and RD must be
held LOW for at least 25ns following BUSY HIGH. Data
will be valid 30ns after the falling edge of both CS and RD.
The output data will remain valid for 20ns following the
rising edge of both CS and RD (see Figure 2 for the read
cycle timing diagram).
FIGURE 2. ADS7852 Write/Read Timing.
DIGITAL OUTPUT
STRAIGHT BINARY
DESCRIPTION ANALOG INPUT BINARY CODE HEX CODE
Least Significant 1.2207mV
Bit (LSB)
Full Scale 4.99878V 1111 1111 1111 FFF
Midscale 2.5V 1000 0000 0000 800
Midscale –1LSB 2.49878V 0111 1111 1111 7FF
Zero Full Scale 0V 0000 0000 0000 000
Table I. Ideal Input Voltages and Output Codes.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
CONV
Conversion Time 1.75 µs
t
ACQ
Acquisition Time 0.25 µs
t
CKP
Clock Period 125 5000 ns
t
CKL
Clock LOW 40 ns
t
CKH
Clock HIGH 40 ns
t
1
WR LOW Prior to Rising Edge of CLK 35 ns
t
2
WR LOW After Rising Edge of CLK 20 ns
t
3
CS LOW After Rising Edge of CLK 20 ns
t
4
CS and RD HIGH 25 ns
t
5
BUSY Delay After CS LOW 20 ns
t
6
RD LOW 25 ns
t
7
Address Hold Time 5 ns
t
8
Address Setup Time 5 ns
t
9
Bus Access Time 30 ns
t
10
Bus Relinquish Time 5 ns
t
11
CS to RD Setup Time 0 ns
t
12
RD to CS Hold Time 0 ns
t
13
CLK LOW to BUSY HIGH 10 ns
t
14
BUSY to RD Delay 0 ns
t
15
RD HIGH to CLK LOW 50 ns
123456789 10 11 12 13 14 15 16 123456789 10 11 12 13 14 15 16 12345678
CLK
HOLD
WR
CS
BUSY
RD
Address
Bus
Data
Bus
t
CKH
t
CKL
t
2
t
4
t
4
t
1
t
3
t
CONV
t
ACQ
t
CKP
Conversion n
Address n + 1 Address n + 2
Conversion n + 1
Hi-ZHi-Z Hi-Z
Data
Valid
Data
Valid
t
5
t
10
t
6
t
8
t
7
t
9