Datasheet

ADS7846
14
SBAS125H
www.ti.com
16 Clocks-per-Conversion
The control bits for conversion n + 1 can be overlapped with
conversion n to allow for a conversion every 16 clock cycles,
as shown in Figure 10. This figure also shows possible serial
communication occurring with other serial peripherals be-
tween each byte transfer from the processor to the converter.
This is possible provided that each conversion completes
within 1.6ms of starting. Otherwise, the signal that is cap-
tured on the input sample-and-hold may droop enough to
affect the conversion result. Note that the ADS7846 is fully
powered while other serial communications are taking place
during a conversion.
Digital Timing
Figures 9, 11, and Table VI provide detailed timing for the
digital interface of the ADS7846.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
ACQ
Acquisition Time 1.5 µs
t
DS
DIN Valid Prior to DCLK Rising 100 ns
t
DH
DIN Hold After DCLK High 10 ns
t
DO
DCLK Falling to DOUT Valid 200 ns
t
DV
CS
Falling to DOUT Enabled 200 ns
t
TR
CS
Rising to DOUT Disabled 200 ns
t
CSS
CS
Falling to First DCLK Rising 100 ns
t
CSH
CS
Rising to DCLK Ignored 0 ns
t
CH
DCLK High 200 ns
t
CL
DCLK Low 200 ns
t
BD
DCLK Falling to BUSY Rising 200 ns
t
BDV
CS
Falling to BUSY Enabled 200 ns
t
BTR
CS
Rising to BUSY Disabled 200 ns
TABLE VI. Timing Specifications (+V
CC
= +2.7V and Above,
T
A
= –40°C to +85°C, C
LOAD
= 50pF).
PD0
t
BDV
t
DH
t
CH
t
CL
t
DS
t
CSS
t
DV
t
BD
t
BD
t
TR
t
BTR
t
D0
t
CSH
DCLK
CS
11DOUT
BUSY
DIN
10
FIGURE 11. Detailed Timing Diagram.
FIGURE 10. Conversion Timing, 16 Clocks-per-Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated
serial port.
1
DCLK
CS
81
11
DOUT
BUSY
SDIN
Control Bits
S
Control Bits
1098765 43210
11 10 9
81 18