Datasheet

®
10
ADS7845
16 Clocks per Conversion
The control bits for conversion n+1 can be overlapped with
conversion ‘n’ to allow for a conversion every 16 clock
cycles, as shown in Figure 6. This figure also shows possible
serial communication occurring with other serial peripherals
between each byte transfer between the processor and the
converter. This is possible provided that each conversion
completes within 1.6ms of starting. Otherwise, the signal
that has been captured on the input sample/hold may droop
enough to affect the conversion result. Note that the ADS7845
is fully powered while other serial communications are
taking place during a conversion.
Digital Timing
Figure 7 and Table VI provide detailed timing for the digital
interface of the ADS7845.
15 Clocks per Conversion
Figure 8 provides the fastest way to clock the ADS7845.
This method will not work with the serial interface of most
microcontrollers and digital signal processors as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method could be used with Field
Programmable Gate Arrays (FPGAs) or Application Spe-
cific Integrated Circuits (ASICs). This effectively increases
the maximum conversion rate of the converter beyond the
values given in the Specification table, which assume 16
clock cycles per conversion.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
ACQ
Acquisition Time 1.5 µs
t
DS
DIN Valid Prior to DCLK Rising 100 ns
t
DH
DIN Hold After DCLK HIGH 10 ns
t
DO
DCLK Falling to DOUT Valid 200 ns
t
DV
CS Falling to DOUT Enabled 200 ns
t
TR
CS Rising to DOUT Disabled 200 ns
t
CSS
CS Falling to First DCLK Rising 100 ns
t
CSH
CS Rising to DCLK Ignored 0 ns
t
CH
DCLK HIGH 200 ns
t
CL
DCLK LOW 200 ns
t
BD
DCLK Falling to BUSY Rising 200 ns
t
BDV
CS Falling to BUSY Enabled 200 ns
t
BTR
CS Rising to BUSY Disabled 200 ns
TABLE VI. Timing Specifications (+V
CC
= +2.7V and
Above, T
A
= –40°C to +85°C, C
LOAD
= 50pF).
FIGURE 7. Detailed Timing Diagram.
FIGURE 8. Maximum Conversion Rate, 15 Clocks per Conversion.
PD0
t
BDV
t
DH
t
CH
t
CL
t
DS
t
CSS
t
DV
t
BD
t
BD
t
TR
t
BTR
t
D0
t
CSH
DCLK
CS
11 DOUT
BUSY
DIN
10
1
DCLK
CS
11 DOUT
BUSY
A2S DIN A1 A0 MODE
SGL/
DIF
PD1 PD0
109876543210 111098765432
A1 A0
15 1 15 1
A2SA1A0 MODE
SGL/
DIF
PD1 PD0 A2S