Datasheet
ADS7844
12
SBAS100A
www.ti.com
Digital Timing
Figure 5 and Tables VI and VII provide detailed timing for
the digital interface of the ADS7844.
15-Clocks per Conversion
Figure 6 provides the fastest way to clock the ADS7844.
This method will not work with the serial interface of most
microcontrollers and digital signal processors as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method could be used with field
programmable gate arrays (FPGAs) or application specific
integrated circuits (ASICs). Note that this effectively in-
creases the maximum conversion rate of the converter be-
yond the values given in the specification tables, which
assume 16 clock cycles per conversion.
PD1 PD0 Description
0 0 Power-down between conversions. When each
conversion is finished, the converter enters a low
power mode. At the start of the next conversion,
the device instantly powers up to full power. There
is no need for additional delays to assure full
operation and the very first conversion is valid.
0 1 Reserved for future use.
1 0 Reserved for future use.
1 1 No power-down between conversions, device al-
ways powered.
TABLE V. Power-Down Selection.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
ACQ
Acquisition Time 1.5 µs
t
DS
DIN Valid Prior to DCLK Rising 100 ns
t
DH
DIN Hold After DCLK HIGH 10 ns
t
DO
DCLK Falling to DOUT Valid 200 ns
t
DV
CS Falling to DOUT Enabled 200 ns
t
TR
CS Rising to DOUT Disabled 200 ns
t
CSS
CS Falling to First DCLK Rising 100 ns
t
CSH
CS Rising to DCLK Ignored 0 ns
t
CH
DCLK HIGH 200 ns
t
CL
DCLK LOW 200 ns
t
BD
DCLK Falling to BUSY Rising 200 ns
t
BDV
CS Falling to BUSY Enabled 200 ns
t
BTR
CS Rising to BUSY Disabled 200 ns
TABLE VI. Timing Specifications (+V
CC
= +2.7V to 3.6V,
T
A
= –40°C to +85°C, C
LOAD
= 50pF).
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
ACQ
Acquisition Time 900 ns
t
DS
DIN Valid Prior to DCLK Rising 50 ns
t
DH
DIN Hold After DCLK HIGH 10 ns
t
DO
DCLK Falling to DOUT Valid 100 ns
t
DV
CS Falling to DOUT Enabled 70 ns
t
TR
CS Rising to DOUT Disabled 70 ns
t
CSS
CS Falling to First DCLK Rising 50 ns
t
CSH
CS Rising to DCLK Ignored 0 ns
t
CH
DCLK HIGH 150 ns
t
CL
DCLK LOW 150 ns
t
BD
DCLK Falling to BUSY Rising 100 ns
t
BDV
CS Falling to BUSY Enabled 70 ns
t
BTR
CS Rising to BUSY Disabled 70 ns
TABLE VII. Timing Specifications (+V
CC
= +4.75V to
+5.25V, T
A
= –40°C to +85°C, C
LOAD
= 50pF).
FIGURE 6. Maximum Conversion Rate, 15-Clocks per Conversion.
FIGURE 5. Detailed Timing Diagram.
PD0
t
BDV
t
DH
t
CH
t
CL
t
DS
t
CSS
t
DV
t
BD
t
BD
t
TR
t
BTR
t
D0
t
CSH
DCLK
CS
11
DOUT
BUSY
DIN
10
1
DCLK
CS
11DOUT
BUSY
A2SDIN A1 A0
SGL/
DIF
PD1 PD0
109876543210 111098765432
A1 A0
15 1 15 1
A2SA1A0
SGL/
DIF
PD1 PD0
A2S